cfg_clock_default.h File Reference
CPU » STM32

Default STM32L4 clock configuration. More...

Detailed Description

Default STM32L4 clock configuration.

Author
Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de
Alexandre Abadie alexa.nosp@m.ndre.nosp@m..abad.nosp@m.ie@i.nosp@m.nria..nosp@m.fr

Definition in file cfg_clock_default.h.

#include "cfg_clock_common_lx_u5_wx.h"
#include "kernel_defines.h"
#include "macros/units.h"
+ Include dependency graph for cfg_clock_default.h:

Go to the source code of this file.

L4/L5/WB clock system configuration

#define CONFIG_CLOCK_PLL_SRC_MSI   1 /* Use MSI as input clock by default */
 
#define CONFIG_CLOCK_PLL_SRC_HSE   0
 
#define CONFIG_CLOCK_PLL_SRC_HSI   0
 
#define CLOCK_PLL_SRC   (CONFIG_CLOCK_HSI)
 
#define CONFIG_CLOCK_PLL_M   (2) /* HSI at 16MHz */
 
#define CONFIG_CLOCK_PLL_N   (20)
 
#define CONFIG_CLOCK_PLL_Q   (2)
 
#define CONFIG_CLOCK_PLL_R   (2)
 
#define CLOCK_AHB   CLOCK_CORECLOCK /* HCLK, max: 48/64/80/120MHz */
 
#define CONFIG_CLOCK_APB1_DIV   (4)
 
#define CLOCK_APB1   (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48/64/80/120MHz */
 
#define CONFIG_CLOCK_APB2_DIV   (2)
 
#define CLOCK_APB2   (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 48/64/80/120MHz */