cpu_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universität Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
23 #include "cpu_conf_common.h"
24 
25 #if defined(CPU_SAMD10)
26 # include "vendor/samd10/include/samd10.h"
27 #elif defined(CPU_SAMD20)
28 # include "vendor/samd20/include/samd20.h"
29 #elif defined(CPU_SAMD20B)
30 # include "vendor/samd20/include_b/samd20.h"
31 #elif defined(CPU_SAMD21A)
32 # include "vendor/samd21/include_a/samd21.h"
33 #elif defined(CPU_SAMD21B)
34 # include "vendor/samd21/include_b/samd21.h"
35 #elif defined(CPU_SAMD21C)
36 # include "vendor/samd21/include_c/samd21.h"
37 #elif defined(CPU_SAMD21D)
38 # include "vendor/samd21/include_d/samd21.h"
39 #elif defined(CPU_SAMD51)
40 # include "vendor/samd51/include/samd51.h"
41 #elif defined(CPU_SAME51)
42 # include "vendor/same51/include/same51.h"
43 #elif defined(CPU_SAME54)
44 # include "vendor/same54/include/same54.h"
45 #elif defined(CPU_SAML10)
46 # include "vendor/saml10/include/sam.h"
47 #elif defined(CPU_SAML11)
48 # include "vendor/saml11/include/sam.h"
49 #elif defined(CPU_SAML21A)
50 # include "vendor/saml21/include/saml21.h"
51 #elif defined(CPU_SAML21B)
52 # include "vendor/saml21/include_b/saml21.h"
53 #elif defined(CPU_SAMR21)
54 # include "vendor/samr21/include/samr21.h"
55 #elif defined(CPU_SAMR30)
56 # include "vendor/samr30/include/samr30.h"
57 #elif defined(CPU_SAMR34)
58 # include "vendor/samr34/include/samr34.h"
59 #endif
60 
61 #ifdef __cplusplus
62 extern "C" {
63 #endif
64 
69 #define CPU_DEFAULT_IRQ_PRIO (1U)
70 #define CPU_IRQ_NUMOF PERIPH_COUNT_IRQn
71 #define CPU_FLASH_BASE FLASH_ADDR
72 
73 #ifdef CPU_COMMON_SAML1X
74 # define CPU_FLASH_RWWEE_BASE DATAFLASH_ADDR
75 #else
76 # define CPU_FLASH_RWWEE_BASE NVMCTRL_RWW_EEPROM_ADDR
77 #endif
84 /* a flashpage in RIOT is mapped to a flash row on the SAM0s */
85 #if defined(NVMCTRL_ROW_SIZE)
86 # define FLASHPAGE_SIZE (NVMCTRL_ROW_SIZE)
87 #elif defined(NVMCTRL_BLOCK_SIZE)
88 # define FLASHPAGE_SIZE (NVMCTRL_BLOCK_SIZE)
89 #elif defined(NVMCTRL_PAGE_SIZE)
90 /* saml1x: The NVM is organized into rows, where each row contains four pages,
91 as shown in the NVM Row Organization figure. */
92 # define FLASHPAGE_SIZE (4 * NVMCTRL_PAGE_SIZE)
93 #else
94 # error "Unsupported Device"
95 #endif
96 
97 /* one SAM0 row contains 4 SAM0 pages, so 4 SAM0 pages contain
98  * the amount of a RIOT flashpage
99  */
100 #define FLASHPAGE_PAGES_PER_ROW (FLASHPAGE_SIZE/FLASH_PAGE_SIZE)
101 /* number of RIOT flashpages on device */
102 #define FLASHPAGE_NUMOF (FLASH_NB_OF_PAGES / FLASHPAGE_PAGES_PER_ROW)
103 /* The minimum block size which can be written is 16B. However, the erase
104  * block is always FLASHPAGE_SIZE (SAM0 row).
105  */
106 #define FLASHPAGE_WRITE_BLOCK_SIZE (16)
107 /* Writing should be always 4 byte aligned */
108 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4)
109 /* Add RWWEE memory if supported by revision of the chip
110  * On some chips it is called RWW EEPROM while on some DATAFLASH, try to
111  * catch all without relying on the CPU model but on the named defines
112  */
113 #ifdef NVMCTRL_RWW_EEPROM_SIZE
114 # define FLASHPAGE_RWWEE_NUMOF (NVMCTRL_RWWEE_PAGES / FLASHPAGE_PAGES_PER_ROW)
115 #endif
116 #ifdef DATAFLASH_SIZE
117 # define FLASHPAGE_RWWEE_NUMOF (DATAFLASH_NB_OF_PAGES / FLASHPAGE_PAGES_PER_ROW)
118 #endif
124 #ifdef CPU_HAS_BACKUP_RAM
125 # define NUM_HEAPS (2)
126 #endif
127 
128 #ifdef __cplusplus
129 }
130 #endif
131