cpu_conf_cc26xx_cc13xx.h File Reference
Implementation specific CPU configuration options. More...
Detailed Description
Implementation specific CPU configuration options.
Definition in file cpu_conf_cc26xx_cc13xx.h.
#include "kernel_defines.h"#include "cpu_conf_common.h"#include "cc26xx_cc13xx.h"#include "cc26xx_cc13xx_adi.h"#include "cc26xx_cc13xx_ccfg.h"#include "cc26xx_cc13xx_gpio.h"#include "cc26xx_cc13xx_gpt.h"#include "cc26xx_cc13xx_hard_api.h"#include "cc26xx_cc13xx_i2c.h"#include "cc26xx_cc13xx_ioc.h"#include "cc26xx_cc13xx_rfc.h"#include "cc26xx_cc13xx_uart.h"#include "cc26xx_cc13xx_vims.h"#include "cc26xx_cc13xx_wdt.h"
Include dependency graph for cpu_conf_cc26xx_cc13xx.h: This graph shows which files directly or indirectly include this file:Go to the source code of this file.
| #define | CPU_DEFAULT_IRQ_PRIO (1U) |
| ARM Cortex-M specific CPU configuration. | |
| #define | CPU_IRQ_NUMOF IRQN_COUNT |
| #define | CPU_FLASH_BASE FLASH_BASE |
| #define | CONFIG_CC26XX_CC13XX_UPDATE_CCFG 0 |
| CC26xx/CC13xx specific CPU configuration. More... | |
| #define | CONFIG_CC26XX_CC13XX_FORCE_VDDR_HH 0 |
| Force VDDR high setting, enables higher output power but also higher power consumption. More... | |
| #define | CONFIG_CC26XX_CC13XX_GPRAM 0 |
| Enable GPRAM and use 8K VIMS RAM as GPRAM (instead of cache). More... | |
| #define | CONFIG_CC26XX_CC13XX_BL_LEVEL 0x1 |
| This configures the level need to enter the bootloader backdoor at boot time. | |
| #define | CONFIG_CC26XX_CC13XX_BL_PIN 0xFF |
| DIO (pin) number used to enter the bootloader backdoor at boot time. | |
| #define | SET_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 |
| Disable GPRAM. | |
| #define | NUM_HEAPS (2) |
| #define | SET_EXT_LF_CLK_DIO 0x01 |
| Customer Configuration (CCFG) More... | |
| #define | SET_EXT_LF_CLK_RTC_INCREMENT 0x800000 |
The input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC. More... | |
| #define | SET_MODE_CONF_1_TCXO_TYPE 0x01 |
| Selects the TCXO type. More... | |
| #define | SET_MODE_CONF_1_TCXO_MAX_START 0x7F |
| Maximum TCXO startup time in units of 100us. More... | |
| #define | SET_MODE_CONF_1_ALT_DCDC_VMIN 0x8 |
| Minimum voltage for when DC/DC should be used if alternate DC/DC setting is enabled. More... | |
| #define | SET_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 |
| Enable DC/DC dithering if alternate DC/DC setting is enabled. More... | |
| #define | SET_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 |
| Inductor peak current if alternate DC/DC setting is enabled. More... | |
| #define | SET_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 |
| Signed delta value for IBIAS_INIT. | |
| #define | SET_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 |
| Signed delta value for IBIAS_OFFSET. | |
| #define | SET_MODE_CONF_1_XOSC_MAX_START 0x10 |
| Maximum XOSC startup time (worst case) in units of 100us. | |
| #define | SET_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058 |
| Total size of the CCFG in bytes. | |
| #define | SET_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS |
| Reserved by Texas Instruments for future use. More... | |
| #define | SET_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 |
| Disable TCXO. More... | |
| #define | SET_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 |
| Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). More... | |
| #define | SET_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 |
| Disable XOSC override functionality. More... | |
| #define | SET_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF |
| Signed delta value to apply to the VDDR_TRIM_SLEEP target, minus one. More... | |
| #define | SET_MODE_CONF_DCDC_RECHARGE 0x0 |
| DC/DC during recharge in powerdown. More... | |
| #define | SET_MODE_CONF_DCDC_ACTIVE 0x0 |
| DC/DC in active mode. More... | |
| #define | SET_MODE_CONF_VDDR_EXT_LOAD 0x0 |
| Reserved for future use byte TI. More... | |
| #define | SET_MODE_CONF_VDDS_BOD_LEVEL 0x1 |
| VDDS BOD level. More... | |
| #define | SET_MODE_CONF_SCLK_LF_OPTION 0x2 |
| LF clock option. More... | |
| #define | SET_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 |
| VDDR_TRIM_SLEEP_DELTA temperature compensation. More... | |
| #define | SET_MODE_CONF_RTC_COMP 0x1 |
| Reserved for future use by TI. | |
| #define | SET_MODE_CONF_XOSC_FREQ 0x2 |
| External crystal frequency. More... | |
| #define | SET_MODE_CONF_XOSC_CAP_MOD 0x1 |
| Enable modification (delta) to XOSC cap-array. More... | |
| #define | SET_MODE_CONF_HF_COMP 0x1 |
| Reserved for future use by TI. | |
| #define | SET_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF |
| Modifies trimmed XOSC cap-array step value. More... | |
| #define | SET_MODE_CONF_VDDR_CAP 0x3A |
| Represents the minimum decoupling capacitance (worst case) on VDDR, in units of 100nF. More... | |
| #define | SET_BL_CONFIG_BOOTLOADER_ENABLE 0x00 |
| Bootloader enable. More... | |
| #define | SET_BL_CONFIG_BL_LEVEL 0x1 |
| Sets the active level of the selected DIO number BL_PIN_NUMBER if boot loader backdoor is enabled by the BL_ENABLE field. More... | |
| #define | SET_BL_CONFIG_BL_PIN_NUMBER 0xFF |
| DIO number that is level checked if the boot loader backdoor is enabled by the SET_BL_CONFIG_BL_ENABLE setting. | |
| #define | SET_BL_CONFIG_BL_ENABLE 0xFF |
| Enables the boot loader backdoor. More... | |
| #define | SET_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 |
| Enable CPU DAP. More... | |
| #define | SET_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5 |
| Enable PWRPROF TAP (PRCM on x0 CPUs). More... | |
| #define | SET_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 |
| Enable Test TAP. More... | |
