cfg_clock_default_120.h
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1 /*
2  * Copyright (C) 2018 Freie Universität Berlin
3  * 2017 OTA keys S.A.
4  * 2018-2020 Inria
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H
24 #define CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H
25 
26 #include "kernel_defines.h"
27 #include "macros/units.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
37 /* The following parameters configure a 120MHz system clock with HSE (8MHz or
38  16MHz) or HSI (16MHz) as PLL input clock */
39 #ifndef CONFIG_CLOCK_PLL_M
40 #define CONFIG_CLOCK_PLL_M (4)
41 #endif
42 #ifndef CONFIG_CLOCK_PLL_N
43 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
44 #define CONFIG_CLOCK_PLL_N (120)
45 #else
46 #define CONFIG_CLOCK_PLL_N (60)
47 #endif
48 #endif
49 #ifndef CONFIG_CLOCK_PLL_P
50 #define CONFIG_CLOCK_PLL_P (2)
51 #endif
52 #ifndef CONFIG_CLOCK_PLL_Q
53 #define CONFIG_CLOCK_PLL_Q (5)
54 #endif
61 #ifndef CONFIG_CLOCK_APB1_DIV
62 #define CONFIG_CLOCK_APB1_DIV (4) /* max 30MHz */
63 #endif
64 #ifndef CONFIG_CLOCK_APB2_DIV
65 #define CONFIG_CLOCK_APB2_DIV (2) /* max 60MHz */
66 #endif
69 #if CLOCK_CORECLOCK > MHZ(120)
70 #error "SYSCLK cannot exceed 120MHz"
71 #endif
72 
73 #ifdef __cplusplus
74 }
75 #endif
76 
77 #endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_120_H */
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.
units.h
Unit helper macros.