cfg_clock_default_216.h
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1 /*
2  * Copyright (C) 2018 Freie Universität Berlin
3  * 2017 OTA keys S.A.
4  * 2018-2020 Inria
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
24 #define CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
25 
26 #include "kernel_defines.h"
27 #include "macros/units.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
37 /* The following parameters configure a 216MHz system clock with HSE (8MHz,
38  16MHz or 25MHz) or HSI (16MHz) as PLL input clock */
39 #ifndef CONFIG_CLOCK_PLL_M
40 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
41 #define CONFIG_CLOCK_PLL_M (25)
42 #else
43 #define CONFIG_CLOCK_PLL_M (4)
44 #endif
45 #endif
46 #ifndef CONFIG_CLOCK_PLL_N
47 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
48 #define CONFIG_CLOCK_PLL_N (432)
49 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
50 #define CONFIG_CLOCK_PLL_N (216)
51 #else
52 #define CONFIG_CLOCK_PLL_N (108)
53 #endif
54 #endif
55 #ifndef CONFIG_CLOCK_PLL_P
56 #define CONFIG_CLOCK_PLL_P (2)
57 #endif
58 #ifndef CONFIG_CLOCK_PLL_Q
59 #define CONFIG_CLOCK_PLL_Q (9)
60 #endif
61 #ifndef CONFIG_CLOCK_PLL_R
62 #define CONFIG_CLOCK_PLL_R (8)
63 #endif
70 #ifndef CONFIG_CLOCK_APB1_DIV
71 #define CONFIG_CLOCK_APB1_DIV (4) /* max 54MHz */
72 #endif
73 #ifndef CONFIG_CLOCK_APB2_DIV
74 #define CONFIG_CLOCK_APB2_DIV (2) /* max 108MHz */
75 #endif
78 #if CLOCK_CORECLOCK > MHZ(216)
79 #error "SYSCLK cannot exceed 216MHz"
80 #endif
81 
82 #ifdef __cplusplus
83 }
84 #endif
85 
86 #endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H */
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.
units.h
Unit helper macros.