cfg_i2c1_pb8_pb9.h
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1 /*
2  * Copyright (C) 2018 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CFG_I2C1_PB8_PB9_H
20 #define CFG_I2C1_PB8_PB9_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 static const i2c_conf_t i2c_config[] = {
33  {
34  .dev = I2C1,
35  .speed = I2C_SPEED_NORMAL,
36  .scl_pin = GPIO_PIN(PORT_B, 8),
37  .sda_pin = GPIO_PIN(PORT_B, 9),
38 #if CPU_FAM_STM32F0
39  .scl_af = GPIO_AF1,
40  .sda_af = GPIO_AF1,
41 #elif CPU_FAM_STM32G0 || CPU_FAM_STM32C0
42  .scl_af = GPIO_AF6,
43  .sda_af = GPIO_AF6,
44 #else
45  .scl_af = GPIO_AF4,
46  .sda_af = GPIO_AF4,
47 #endif
48  .bus = APB1,
49 #if CPU_FAM_STM32F4 || CPU_FAM_STM32F2
50  .rcc_mask = RCC_APB1ENR_I2C1EN,
51  .clk = CLOCK_APB1,
52  .irqn = I2C1_EV_IRQn,
53 #elif CPU_FAM_STM32L4 || CPU_FAM_STM32WB || CPU_FAM_STM32G4
54  .rcc_mask = RCC_APB1ENR1_I2C1EN,
55  .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
56  .irqn = I2C1_ER_IRQn,
57 #elif CPU_FAM_STM32L5
58  .rcc_mask = RCC_APB1ENR1_I2C1EN,
59  .rcc_sw_mask = RCC_CCIPR1_I2C1SEL_1, /* HSI (16 MHz) */
60  .irqn = I2C1_ER_IRQn,
61 #elif CPU_FAM_STM32G0 || CPU_FAM_STM32C0
62  .rcc_mask = RCC_APBENR1_I2C1EN,
63  .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
64  .irqn = I2C1_IRQn,
65 #elif CPU_FAM_STM32F7
66  .rcc_mask = RCC_APB1ENR_I2C1EN,
67  .rcc_sw_mask = RCC_DCKCFGR2_I2C1SEL_1, /* HSI (16 MHz) */
68  .irqn = I2C1_ER_IRQn,
69 #elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0
70  .rcc_mask = RCC_APB1ENR_I2C1EN,
71 #if CPU_FAM_STM32F0
72  .rcc_sw_mask = RCC_CFGR3_I2C1SW,
73 #endif
74  .irqn = I2C1_IRQn,
75 #endif
76  }
77 };
78 
79 #if CPU_FAM_STM32F4 || CPU_FAM_STM32F2
80 #define I2C_0_ISR isr_i2c1_ev
81 #elif CPU_FAM_STM32L4 || CPU_FAM_STM32F7 || CPU_FAM_STM32WB || CPU_FAM_STM32L5
82 #define I2C_0_ISR isr_i2c1_er
83 #elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0 || CPU_FAM_STM32G0 || CPU_FAM_STM32C0
84 #define I2C_0_ISR isr_i2c1
85 #endif
86 
87 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
90 #ifdef __cplusplus
91 }
92 #endif
93 
94 #endif /* CFG_I2C1_PB8_PB9_H */
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:48
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
GPIO_AF1
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:103
GPIO_AF4
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:106
GPIO_AF6
@ GPIO_AF6
use alternate function 6
Definition: cpu_gpio.h:108
APB1
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
I2C_SPEED_NORMAL
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:278
CLOCK_APB1
#define CLOCK_APB1
Half AHB clock.
Definition: periph_common_conf.h:41
i2c_conf_t
I2C configuration structure.
Definition: periph_cpu.h:299
i2c_conf_t::dev
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:300