cpu_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universität Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef CPU_CONF_H
22 #define CPU_CONF_H
23 
24 #include "cpu_conf_common.h"
25 
26 #if defined(CPU_SAMD10)
27 #include "vendor/samd10/include/samd10.h"
28 #elif defined(CPU_SAMD20)
29 #include "vendor/samd20/include/samd20.h"
30 #elif defined(CPU_SAMD20B)
31 #include "vendor/samd20/include_b/samd20.h"
32 #elif defined(CPU_SAMD21A)
33 #include "vendor/samd21/include_a/samd21.h"
34 #elif defined(CPU_SAMD21B)
35 #include "vendor/samd21/include_b/samd21.h"
36 #elif defined(CPU_SAMD21C)
37 #include "vendor/samd21/include_c/samd21.h"
38 #elif defined(CPU_SAMD21D)
39 #include "vendor/samd21/include_d/samd21.h"
40 #elif defined(CPU_SAMD51)
41 #include "vendor/samd51/include/samd51.h"
42 #elif defined(CPU_SAME51)
43 #include "vendor/same51/include/same51.h"
44 #elif defined(CPU_SAME54)
45 #include "vendor/same54/include/same54.h"
46 #elif defined(CPU_SAML10)
47 #include "vendor/saml10/include/sam.h"
48 #elif defined(CPU_SAML11)
49 #include "vendor/saml11/include/sam.h"
50 #elif defined(CPU_SAML21A)
51 #include "vendor/saml21/include/saml21.h"
52 #elif defined(CPU_SAML21B)
53 #include "vendor/saml21/include_b/saml21.h"
54 #elif defined(CPU_SAMR21)
55 #include "vendor/samr21/include/samr21.h"
56 #elif defined(CPU_SAMR30)
57 #include "vendor/samr30/include/samr30.h"
58 #elif defined(CPU_SAMR34)
59 #include "vendor/samr34/include/samr34.h"
60 #endif
61 
62 #ifdef __cplusplus
63 extern "C" {
64 #endif
65 
70 #define CPU_DEFAULT_IRQ_PRIO (1U)
71 #define CPU_IRQ_NUMOF PERIPH_COUNT_IRQn
72 #define CPU_FLASH_BASE FLASH_ADDR
73 
74 #ifdef CPU_COMMON_SAML1X
75 #define CPU_FLASH_RWWEE_BASE DATAFLASH_ADDR
76 #else
77 #define CPU_FLASH_RWWEE_BASE NVMCTRL_RWW_EEPROM_ADDR
78 #endif
85 /* a flashpage in RIOT is mapped to a flash row on the SAM0s */
86 #if defined(NVMCTRL_ROW_SIZE)
87 #define FLASHPAGE_SIZE (NVMCTRL_ROW_SIZE)
88 #elif defined(NVMCTRL_BLOCK_SIZE)
89 #define FLASHPAGE_SIZE (NVMCTRL_BLOCK_SIZE)
90 #elif defined(NVMCTRL_PAGE_SIZE)
91 /* saml1x: The NVM is organized into rows, where each row contains four pages,
92 as shown in the NVM Row Organization figure. */
93 #define FLASHPAGE_SIZE (4 * NVMCTRL_PAGE_SIZE)
94 #else
95 #error "Unsupported Device"
96 #endif
97 
98 /* one SAM0 row contains 4 SAM0 pages, so 4 SAM0 pages contain
99  * the amount of a RIOT flashpage
100  */
101 #define FLASHPAGE_PAGES_PER_ROW (FLASHPAGE_SIZE/FLASH_PAGE_SIZE)
102 /* number of RIOT flashpages on device */
103 #define FLASHPAGE_NUMOF (FLASH_NB_OF_PAGES / FLASHPAGE_PAGES_PER_ROW)
104 /* The minimum block size which can be written is 16B. However, the erase
105  * block is always FLASHPAGE_SIZE (SAM0 row).
106  */
107 #define FLASHPAGE_WRITE_BLOCK_SIZE (16)
108 /* Writing should be always 4 byte aligned */
109 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4)
110 /* Add RWWEE memory if supported by revision of the chip
111  * On some chips it is called RWW EEPROM while on some DATAFLASH, try to
112  * catch all without relying on the CPU model but on the named defines
113  */
114 #ifdef NVMCTRL_RWW_EEPROM_SIZE
115 #define FLASHPAGE_RWWEE_NUMOF (NVMCTRL_RWWEE_PAGES / FLASHPAGE_PAGES_PER_ROW)
116 #endif
117 #ifdef DATAFLASH_SIZE
118 #define FLASHPAGE_RWWEE_NUMOF (DATAFLASH_NB_OF_PAGES / FLASHPAGE_PAGES_PER_ROW)
119 #endif
125 #ifdef CPU_HAS_BACKUP_RAM
126 #define NUM_HEAPS (2)
127 #endif
128 
129 #ifdef __cplusplus
130 }
131 #endif
132 
133 #endif /* CPU_CONF_H */