cpu_conf.h
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1 /*
2  * Copyright (C) 2016 Freie Universität Berlin
3  * 2016 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
21 #ifndef CPU_CONF_H
22 #define CPU_CONF_H
23 
24 #include <stdint.h>
25 #include "cpu_conf_common.h"
26 
27 #if defined(CPU_LINE_STM32F030x4)
28 #include "vendor/stm32f030x4.h"
29 #elif defined(CPU_LINE_STM32MP157Cxx)
30 #include "vendor/stm32mp157cxx_cm4.h"
31 #elif CPU_FAM_STM32F0
32 #include "stm32f0xx.h"
33 #include "irqs/f0/irqs.h"
34 #elif CPU_FAM_STM32F1
35 #include "stm32f1xx.h"
36 #include "irqs/f1/irqs.h"
37 #elif CPU_FAM_STM32F2
38 #include "stm32f2xx.h"
39 #include "irqs/f2/irqs.h"
40 #elif CPU_FAM_STM32F3
41 #include "stm32f3xx.h"
42 #include "irqs/f3/irqs.h"
43 #elif CPU_FAM_STM32F4
44 #include "stm32f4xx.h"
45 #include "irqs/f4/irqs.h"
46 #elif CPU_FAM_STM32F7
47 #include "stm32f7xx.h"
48 #include "irqs/f7/irqs.h"
49 #elif CPU_FAM_STM32G0
50 #include "stm32g0xx.h"
51 #include "irqs/g0/irqs.h"
52 #elif CPU_FAM_STM32C0
53 #include "stm32c0xx.h"
54 #include "irqs/c0/irqs.h"
55 #elif CPU_FAM_STM32G4
56 #include "stm32g4xx.h"
57 #include "irqs/g4/irqs.h"
58 #elif CPU_FAM_STM32L0
59 #include "stm32l0xx.h"
60 #include "irqs/l0/irqs.h"
61 #elif CPU_FAM_STM32L1
62 #include "stm32l1xx.h"
63 #include "irqs/l1/irqs.h"
64 #elif CPU_FAM_STM32L4
65 #include "stm32l4xx.h"
66 #include "irqs/l4/irqs.h"
67 #elif CPU_FAM_STM32L5
68 #include "stm32l5xx.h"
69 #include "irqs/l5/irqs.h"
70 #elif CPU_FAM_STM32U5
71 #include "stm32u5xx.h"
72 #include "irqs/u5/irqs.h"
73 #define NUM_HEAPS 3
74 #elif CPU_FAM_STM32WB
75 #include "stm32wbxx.h"
76 #include "irqs/wb/irqs.h"
77 #elif CPU_FAM_STM32WL
78 #include "stm32wlxx.h"
79 #include "irqs/wl/irqs.h"
80 #else
81 #error Not supported CPU family
82 #endif
83 
84 /* add unused backup RAM as extra heap */
85 #if !defined(NUM_HEAPS) && CPU_HAS_BACKUP_RAM
86 #define NUM_HEAPS 2
87 #endif
88 
89 #ifdef __cplusplus
90 extern "C" {
91 #endif
92 
101 #define CORTEXM_ISB_REQUIRED_AFTER_WFI 1
102 
107 #define CPU_DEFAULT_IRQ_PRIO (1U)
108 /* STM32MP1 family has no flah */
109 #if !defined(CPU_FAM_STM32MP1)
110 #define CPU_FLASH_BASE FLASH_BASE
111 #endif
112 
113 /* CPU_IRQ_NUMOF cannot be determined automatically from cmsis header */
114 #if defined(CPU_LINE_STM32F030x4)
115 #define CPU_IRQ_NUMOF (28U)
116 #elif defined(CPU_MODEL_STM32MP157CAC)
117 #define CPU_IRQ_NUMOF (150U)
118 #endif
125 #if defined(CPU_FAM_STM32U5)
126 #define FLASHPAGE_SIZE (8192U)
127 #elif defined(CPU_FAM_STM32WB)
128 #define FLASHPAGE_SIZE (4096U)
129 #elif defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
130  || defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
131  || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
132  || defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) \
133  || defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) \
134  || defined(CPU_FAM_STM32C0)
135 #define FLASHPAGE_SIZE (2048U)
136 #elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
137  || defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \
138  || defined(CPU_LINE_STM32F030x4) || defined(CPU_LINE_STM32F103xB) \
139  || defined(CPU_LINE_STM32F031x6)
140 #define FLASHPAGE_SIZE (1024U)
141 #elif defined(CPU_FAM_STM32L1)
142 #define FLASHPAGE_SIZE (256U)
143 #elif defined(CPU_FAM_STM32L0)
144 #define FLASHPAGE_SIZE (128U)
145 #endif
146 
147 #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
148 #define FLASHPAGE_ERASE_STATE (0x00U)
149 #endif
150 
151 #ifdef FLASHPAGE_SIZE
152 #define FLASHPAGE_NUMOF (STM32_FLASHSIZE / FLASHPAGE_SIZE)
153 #endif
154 
155 #if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
156  defined(CPU_FAM_STM32F7)
157 #define PERIPH_FLASHPAGE_CUSTOM_PAGESIZES
158 #define PERIPH_FLASHPAGE_NEEDS_FLASHPAGE_ADDR
159 
171 #if (defined(FLASH_OPTCR_DB1M) && (STM32_FLASHSIZE >= (1024 * 1024)))
172 #define FLASHPAGE_DUAL_BANK 1
173 #else
174 #define FLASHPAGE_DUAL_BANK 0
175 #endif
176 
177 /* stm32f7 uses single bank with 32KB to 256KB sectors on a number of devices */
178 #if defined(CPU_FAM_STM32F7)
179 #if defined(CPU_LINE_STM32F745xx) || \
180  defined(CPU_LINE_STM32F746xx) || \
181  defined(CPU_LINE_STM32F750xx) || \
182  defined(CPU_LINE_STM32F756xx) || \
183  defined(CPU_LINE_STM32F765xx) || \
184  defined(CPU_LINE_STM32F767xx) || \
185  defined(CPU_LINE_STM32F769xx) || \
186  defined(CPU_LINE_STM32F777xx) || \
187  defined(CPU_LINE_STM32F779xx)
188 #define FLASHPAGE_MIN_SECTOR_SIZE (32 * 1024)
189 #elif defined(CPU_LINE_STM32F722xx) || \
190  defined(CPU_LINE_STM32F723xx) || \
191  defined(CPU_LINE_STM32F730xx) || \
192  defined(CPU_LINE_STM32F732xx) || \
193  defined(CPU_LINE_STM32F733xx)
194 #define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
195 #else
196 /* Intentionally error on an unknown line to prevent flashpage errors */
197 #error Unknown STM32F7 Line, unable to determine FLASHPAGE_MIN_SECTOR_SIZE
198 #endif
199 
200 #else /* CPU_FAM_STM32F7 */
201 #define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
202 #endif
203 
204 #if FLASHPAGE_DUAL_BANK
205 /* Number of "large" sectors + 4 for the small sectors that together equal a
206  * single large sector. Times two to account for the two banks */
207 #define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
208  (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 8)
209 #else
210 /* Number of "large" sectors + 4 for the small sectors that together equal a
211  * single large sector, eg: 1 MB = 7 * 128 KB sectors + 1 64 KB and 4 16 KB
212  * sectors */
213 #define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
214  (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 4)
215 #endif
216 
217 #endif
218 
219 /* The minimum block size which can be written depends on the family.
220  * However, the erase block is always FLASHPAGE_SIZE.
221  */
222 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
223  defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
224  defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
225  defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
226 #define FLASHPAGE_WRITE_BLOCK_SIZE (8U)
227 typedef uint64_t stm32_flashpage_block_t;
228 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
229  defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
230  defined(CPU_FAM_STM32F7)
231 #define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
232 typedef uint32_t stm32_flashpage_block_t;
233 #else
234 #define FLASHPAGE_WRITE_BLOCK_SIZE (2U)
235 typedef uint16_t stm32_flashpage_block_t;
236 #endif
237 
238 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
239  defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
240  defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
241  defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
242 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (8U)
243 #else
244 /* Writing should be always 4 bytes aligned */
245 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
246 #endif
253 #ifdef SRAM_BB_BASE
254 #define CPU_HAS_BITBAND 1
255 #endif
258 #ifdef __cplusplus
259 }
260 #endif
261 
262 #endif /* CPU_CONF_H */