cfg_clock_default_180.h
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1 /*
2  * SPDX-FileCopyrightText: 2018 Freie Universität Berlin
3  * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4  * SPDX-FileCopyrightText: 2018-2020 Inria
5  * SPDX-License-Identifier: LGPL-2.1-only
6  */
7 
8 #pragma once
9 
22 #include "kernel_defines.h"
23 #include "macros/units.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 /* The following parameters configure a 180MHz system clock with HSE (8MHz,
34  12MHz or 16MHz) or HSI (16MHz) as PLL input clock.
35  If USB is used and no alternative 48MHz is available, the clock frequency is
36  decreased to 168MHZ so the PLLQ can output 48MHz.
37  */
38 #ifndef CONFIG_CLOCK_PLL_M
39 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12))
40 #define CONFIG_CLOCK_PLL_M (12)
41 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(16))
42 #define CONFIG_CLOCK_PLL_M (16)
43 #else
44 #define CONFIG_CLOCK_PLL_M (4)
45 #endif
46 #endif
47 #ifndef CONFIG_CLOCK_PLL_N
48 #if (IS_USED(MODULE_PERIPH_USBDEV_CLK) || IS_USED(MODULE_PERIPH_SDMMC_CLK)) && \
49  (defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
50  defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
51  defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
52  defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx))
53 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
54 #define CONFIG_CLOCK_PLL_N (168)
55 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12) || \
56  (CONFIG_CLOCK_HSE == MHZ(16)))
57 #define CONFIG_CLOCK_PLL_N (336)
58 #else
59 #define CONFIG_CLOCK_PLL_N (84)
60 #endif
61 #else
62 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
63 #define CONFIG_CLOCK_PLL_N (180)
64 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(12) || \
65  (CONFIG_CLOCK_HSE == MHZ(16)))
66 #define CONFIG_CLOCK_PLL_N (360)
67 #else
68 #define CONFIG_CLOCK_PLL_N (90)
69 #endif
70 #endif /* MODULE_PERIPH_USBDEV_CLK || MODULE_PERIPH_SDMMC_CLK */
71 #endif
72 #ifndef CONFIG_CLOCK_PLL_P
73 #define CONFIG_CLOCK_PLL_P (2)
74 #endif
75 #ifndef CONFIG_CLOCK_PLL_Q
76 #if (IS_USED(MODULE_PERIPH_USBDEV_CLK) || IS_USED(MODULE_PERIPH_SDMMC_CLK)) && \
77  (defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
78  defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
79  defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
80  defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx))
81 #define CONFIG_CLOCK_PLL_Q (7)
82 #else
83 #define CONFIG_CLOCK_PLL_Q (8)
84 #endif
85 #endif
86 #ifndef CONFIG_CLOCK_PLL_R
87 #define CONFIG_CLOCK_PLL_R (8)
88 #endif
95 #ifndef CONFIG_CLOCK_APB1_DIV
96 #define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */
97 #endif
98 #ifndef CONFIG_CLOCK_APB2_DIV
99 #define CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */
100 #endif
103 #if CLOCK_CORECLOCK > MHZ(180)
104 #error "SYSCLK cannot exceed 180MHz"
105 #endif
106 
107 #ifdef __cplusplus
108 }
109 #endif
110 
Common macros and compiler attributes/pragmas configuration.
Unit helper macros.