cfg_clock_default_84.h
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1 /*
2  * SPDX-FileCopyrightText: 2018 Freie Universität Berlin
3  * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4  * SPDX-FileCopyrightText: 2018-2020 Inria
5  * SPDX-License-Identifier: LGPL-2.1-only
6  */
7 
8 #pragma once
9 
22 #include "kernel_defines.h"
23 #include "macros/units.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 /* The following parameters configure a 84MHz system clock with HSE (8MHz, 16MHz
34  or 25MHz) or HSI (16MHz) as PLL input clock */
35 #ifndef CONFIG_CLOCK_PLL_M
36 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
37 #define CONFIG_CLOCK_PLL_M (25)
38 #else
39 #define CONFIG_CLOCK_PLL_M (4)
40 #endif
41 #endif
42 #ifndef CONFIG_CLOCK_PLL_N
43 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
44 #define CONFIG_CLOCK_PLL_N (168)
45 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
46 #define CONFIG_CLOCK_PLL_N (336)
47 #else
48 #define CONFIG_CLOCK_PLL_N (84)
49 #endif
50 #endif
51 #ifndef CONFIG_CLOCK_PLL_P
52 #define CONFIG_CLOCK_PLL_P (4)
53 #endif
54 #ifndef CONFIG_CLOCK_PLL_Q
55 #define CONFIG_CLOCK_PLL_Q (7)
56 #endif
57 #ifndef CONFIG_CLOCK_PLL_R
58 #define CONFIG_CLOCK_PLL_R (0)
59 #endif
66 #ifndef CONFIG_CLOCK_APB1_DIV
67 #define CONFIG_CLOCK_APB1_DIV (2) /* max 42MHz */
68 #endif
69 #ifndef CONFIG_CLOCK_APB2_DIV
70 #define CONFIG_CLOCK_APB2_DIV (1) /* max 84MHz */
71 #endif
74 #if CLOCK_CORECLOCK > MHZ(84)
75 #error "SYSCLK cannot exceed 84MHz"
76 #endif
77 
78 #ifdef __cplusplus
79 }
80 #endif
81 
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.
units.h
Unit helper macros.