cfg_clock_default.h
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1 /*
2  * SPDX-FileCopyrightText: 2021 Inria
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
18 #include "cfg_clock_common_lx_u5_wx.h"
19 #include "kernel_defines.h"
20 #include "macros/units.h"
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
30 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48))
31 #error "HSE clock frequency must be between 4MHz and 48MHz"
32 #endif
33 
34 /* The following parameters configure a 80MHz system clock with PLL as input clock */
35 #ifndef CONFIG_CLOCK_PLL_SRC_MSI
36 #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
37  IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
38 #define CONFIG_CLOCK_PLL_SRC_MSI 0
39 #else
40 #define CONFIG_CLOCK_PLL_SRC_MSI 1 /* Use MSI as input clock by default */
41 #endif
42 #endif /* CONFIG_CLOCK_PLL_SRC_MSI */
43 #ifndef CONFIG_CLOCK_PLL_SRC_HSE
44 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && \
45  !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) && !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
46 #define CONFIG_CLOCK_PLL_SRC_HSE 1
47 #else
48 #define CONFIG_CLOCK_PLL_SRC_HSE 0
49 #endif
50 #endif
51 #ifndef CONFIG_CLOCK_PLL_SRC_HSI
52 #define CONFIG_CLOCK_PLL_SRC_HSI 0
53 #endif
54 #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
55 #define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI)
56 #elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE)
57 #define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
58 #else /* CONFIG_CLOCK_PLL_SRC_ */
59 #define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
60 #endif
61 #ifndef CONFIG_CLOCK_PLL_M
62 #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
63 #define CONFIG_CLOCK_PLL_M (6) /* MSI at 48MHz */
64 #else
65 #define CONFIG_CLOCK_PLL_M (2) /* HSI/HSE at 16MHz */
66 #endif
67 #endif
68 #ifndef CONFIG_CLOCK_PLL_N
69 #define CONFIG_CLOCK_PLL_N (40)
70 #endif
71 #ifndef CONFIG_CLOCK_PLL_Q
72 #define CONFIG_CLOCK_PLL_Q (2)
73 #endif
74 #ifndef CONFIG_CLOCK_PLL_R
75 #define CONFIG_CLOCK_PLL_R (2)
76 #endif
77 
78 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
79 #define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
80 
81 #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
82 #define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
83 
84 #elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
85 #define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
86 
87 #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
88 /* PLL configuration: make sure your values are legit!
89  *
90  * compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
91  * with:
92  * PLL_IN: input clock, HSE or MSI
93  * M: pre-divider, allowed range: [1:8]
94  * N: multiplier, allowed range: [5:512]
95  * R: post-divider, allowed range: [2:8]
96  *
97  * Also the following constraints need to be met:
98  * (PLL_IN / M) -> [4MHz:16MHz]
99  * (PLL_IN / M) * N -> [64MHz:344MHz]
100  * CORECLOCK -> 64MHz, 80MHZ or 120MHz MAX!
101  */
102 #define CLOCK_CORECLOCK \
103  ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
104 
105 /* Set max allowed sysclk */
106 #define CLOCK_CORECLOCK_MAX MHZ(160)
107 
108 #if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
109 #error "SYSCLK cannot exceed 160MHz"
110 #endif /* CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX */
111 #endif /* CONFIG_USE_CLOCK_PLL */
112 
113 #define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 160MHz */
114 
115 #ifndef CONFIG_CLOCK_APB1_DIV
116 #define CONFIG_CLOCK_APB1_DIV (4)
117 #endif
118 #define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 160MHz */
119 #ifndef CONFIG_CLOCK_APB2_DIV
120 #define CONFIG_CLOCK_APB2_DIV (2)
121 #endif
122 #define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 160MHz */
125 #ifdef __cplusplus
126 }
127 #endif
128 
cfg_clock_common_lx_u5_wx.h
Base STM32Lx/U5/Wx clock configuration.
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.
units.h
Unit helper macros.