periph_cpu.h

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/*
 * SPDX-FileCopyrightText: 2015-2017 Freie Universität Berlin
 * SPDX-FileCopyrightText: 2017 Inria
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#ifndef DOXYGEN
 
#define STM32_BOOTLOADER_ADDR   (0x1FF00000)
 
#define HAVE_ADC_RES_T
typedef enum {
    ADC_RES_6BIT  = (ADC_CFGR1_RES),    
    ADC_RES_8BIT  = (ADC_CFGR1_RES_1),  
    ADC_RES_10BIT = (ADC_CFGR1_RES_0),  
    ADC_RES_12BIT = (0x00),             
    ADC_RES_14BIT = (0xfe),     
    ADC_RES_16BIT = (0xff)      
} adc_res_t;
#endif /* ndef DOXYGEN */
 
#define EEPROM_START_ADDR          (0x08080000)
#if defined(CPU_LINE_STM32L073xx) || defined(CPU_LINE_STM32L072xx)
#define EEPROM_SIZE                (6144U)  /* 6kB */
#elif defined(CPU_LINE_STM32L053xx) || defined(CPU_LINE_STM32L052xx)
#define EEPROM_SIZE                (2048U)  /* 2kB */
#elif defined(CPU_LINE_STM32L031xx)
#define EEPROM_SIZE                (1024U)  /* 1kB */
#elif defined(CPU_LINE_STM32L010xB) || defined(CPU_LINE_STM32L011x3) || \
      defined(CPU_LINE_STM32L011x4) || defined(CPU_LINE_STM32L021x4) || \
      defined(CPU_MODEL_STM32L011K4)
#define EEPROM_SIZE                (512U)   /* 512B */
#elif defined(CPU_LINE_STM32L010x6) || defined(CPU_LINE_STM32L010x8)
#define EEPROM_SIZE                (256U)   /* 256B */
#elif defined(CPU_LINE_STM32L010x4)
#define EEPROM_SIZE                (128U)   /* 128B */
#endif
#ifdef __cplusplus
}
#endif