cpu_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2014-2016 Freie Universität Berlin
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
20 #include "cpu_conf_common.h"
21 
22 #if defined(CPU_SAMD10)
23 # include "vendor/samd10/include/samd10.h"
24 #elif defined(CPU_SAMD20)
25 # include "vendor/samd20/include/samd20.h"
26 #elif defined(CPU_SAMD20B)
27 # include "vendor/samd20/include_b/samd20.h"
28 #elif defined(CPU_SAMD21A)
29 # include "vendor/samd21/include_a/samd21.h"
30 #elif defined(CPU_SAMD21B)
31 # include "vendor/samd21/include_b/samd21.h"
32 #elif defined(CPU_SAMD21C)
33 # include "vendor/samd21/include_c/samd21.h"
34 #elif defined(CPU_SAMD21D)
35 # include "vendor/samd21/include_d/samd21.h"
36 #elif defined(CPU_SAMD51)
37 # include "vendor/samd51/include/samd51.h"
38 #elif defined(CPU_SAME51)
39 # include "vendor/same51/include/same51.h"
40 #elif defined(CPU_SAME54)
41 # include "vendor/same54/include/same54.h"
42 #elif defined(CPU_SAML10)
43 # include "vendor/saml10/include/sam.h"
44 #elif defined(CPU_SAML11)
45 # include "vendor/saml11/include/sam.h"
46 #elif defined(CPU_SAML21A)
47 # include "vendor/saml21/include/saml21.h"
48 #elif defined(CPU_SAML21B)
49 # include "vendor/saml21/include_b/saml21.h"
50 #elif defined(CPU_SAMR21)
51 # include "vendor/samr21/include/samr21.h"
52 #elif defined(CPU_SAMR30)
53 # include "vendor/samr30/include/samr30.h"
54 #elif defined(CPU_SAMR34)
55 # include "vendor/samr34/include/samr34.h"
56 #endif
57 
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61 
66 #define CPU_DEFAULT_IRQ_PRIO (1U)
67 #define CPU_IRQ_NUMOF PERIPH_COUNT_IRQn
68 #define CPU_FLASH_BASE FLASH_ADDR
69 
70 #ifdef CPU_COMMON_SAML1X
71 # define CPU_FLASH_RWWEE_BASE DATAFLASH_ADDR
72 #else
73 # define CPU_FLASH_RWWEE_BASE NVMCTRL_RWW_EEPROM_ADDR
74 #endif
81 /* a flashpage in RIOT is mapped to a flash row on the SAM0s */
82 #if defined(NVMCTRL_ROW_SIZE)
83 # define FLASHPAGE_SIZE (NVMCTRL_ROW_SIZE)
84 #elif defined(NVMCTRL_BLOCK_SIZE)
85 # define FLASHPAGE_SIZE (NVMCTRL_BLOCK_SIZE)
86 #elif defined(NVMCTRL_PAGE_SIZE)
87 /* saml1x: The NVM is organized into rows, where each row contains four pages,
88 as shown in the NVM Row Organization figure. */
89 # define FLASHPAGE_SIZE (4 * NVMCTRL_PAGE_SIZE)
90 #else
91 # error "Unsupported Device"
92 #endif
93 
94 /* one SAM0 row contains 4 SAM0 pages, so 4 SAM0 pages contain
95  * the amount of a RIOT flashpage
96  */
97 #define FLASHPAGE_PAGES_PER_ROW (FLASHPAGE_SIZE/FLASH_PAGE_SIZE)
98 /* number of RIOT flashpages on device */
99 #define FLASHPAGE_NUMOF (FLASH_NB_OF_PAGES / FLASHPAGE_PAGES_PER_ROW)
100 /* The minimum block size which can be written is 16B. However, the erase
101  * block is always FLASHPAGE_SIZE (SAM0 row).
102  */
103 #define FLASHPAGE_WRITE_BLOCK_SIZE (16)
104 /* Writing should be always 4 byte aligned */
105 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4)
106 /* Add RWWEE memory if supported by revision of the chip
107  * On some chips it is called RWW EEPROM while on some DATAFLASH, try to
108  * catch all without relying on the CPU model but on the named defines
109  */
110 #ifdef NVMCTRL_RWW_EEPROM_SIZE
111 # define FLASHPAGE_RWWEE_NUMOF (NVMCTRL_RWWEE_PAGES / FLASHPAGE_PAGES_PER_ROW)
112 #endif
113 #ifdef DATAFLASH_SIZE
114 # define FLASHPAGE_RWWEE_NUMOF (DATAFLASH_NB_OF_PAGES / FLASHPAGE_PAGES_PER_ROW)
115 #endif
121 #ifdef CPU_HAS_BACKUP_RAM
122 # define NUM_HEAPS (2)
123 #endif
124 
125 #ifdef __cplusplus
126 }
127 #endif
128