periph_conf.h
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1 /*
2  * Copyright (C) 2020 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
9 #pragma once
10 
21 #include "periph_cpu.h"
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
31 #ifndef CLOCK_CORECLOCK
32 #define CLOCK_CORECLOCK MHZ(120)
33 #endif
40 #define EXTERNAL_OSC32_SOURCE 0
41 #define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE 1
48 #define USE_VREG_BUCK (1)
49 
54 static const tc32_conf_t timer_config[] = {
55  { /* Timer 0 - System Clock */
56  .dev = TC0,
57  .irq = TC0_IRQn,
58  .mclk = &MCLK->APBAMASK.reg,
59  .mclk_mask = MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1,
60  .gclk_id = TC0_GCLK_ID,
61  .gclk_src = SAM0_GCLK_TIMER,
62  .flags = TC_CTRLA_MODE_COUNT32,
63  },
64  { /* Timer 1 */
65  .dev = TC2,
66  .irq = TC2_IRQn,
67  .mclk = &MCLK->APBBMASK.reg,
68  .mclk_mask = MCLK_APBBMASK_TC2 | MCLK_APBBMASK_TC3,
69  .gclk_id = TC2_GCLK_ID,
70  .gclk_src = SAM0_GCLK_TIMER,
71  .flags = TC_CTRLA_MODE_COUNT32,
72  }
73 };
74 
75 /* Timer 0 configuration */
76 #define TIMER_0_CHANNELS 2
77 #define TIMER_0_ISR isr_tc0
78 
79 /* Timer 1 configuration */
80 #define TIMER_1_CHANNELS 2
81 #define TIMER_1_ISR isr_tc2
82 
83 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
90 static const uart_conf_t uart_config[] = {
91  { /* Virtual COM Port */
92  .dev = &SERCOM5->USART,
93  .rx_pin = GPIO_PIN(PB, 16),
94  .tx_pin = GPIO_PIN(PB, 17),
95 #ifdef MODULE_SAM0_PERIPH_UART_HW_FC
96  .rts_pin = GPIO_UNDEF,
97  .cts_pin = GPIO_UNDEF,
98 #endif
99  .mux = GPIO_MUX_C,
100  .rx_pad = UART_PAD_RX_1,
101  .tx_pad = UART_PAD_TX_0,
102  .flags = UART_FLAG_NONE,
103  .gclk_src = SAM0_GCLK_PERIPH,
104  }
105 };
106 
107 /* interrupt function name mapping */
108 #define UART_0_ISR isr_sercom5_2
109 #define UART_0_ISR_TX isr_sercom5_0
110 
111 #define UART_NUMOF ARRAY_SIZE(uart_config)
118 #define PWM_0_EN 1
119 
120 #if PWM_0_EN
121 /* PWM0 channels */
122 static const pwm_conf_chan_t pwm_chan0_config[] = {
123  /* GPIO pin, MUX value, TCC channel */
124  { GPIO_PIN(PA, 22), GPIO_MUX_G, 2 },
125 };
126 #endif
127 
128 /* PWM device configuration */
129 static const pwm_conf_t pwm_config[] = {
130 #if PWM_0_EN
131  { .tim = TCC_CONFIG(TCC0),
132  .chan = pwm_chan0_config,
133  .chan_numof = ARRAY_SIZE(pwm_chan0_config),
134  .gclk_src = SAM0_GCLK_PERIPH,
135  },
136 #endif
137 };
138 
139 /* number of devices that are actually defined */
140 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
147 static const spi_conf_t spi_config[] = {
148  {
149  .dev = &(SERCOM1->SPI),
150  .miso_pin = GPIO_PIN(PB, 22),
151  .mosi_pin = GPIO_PIN(PB, 23),
152  .clk_pin = GPIO_PIN(PA, 17),
153  .miso_mux = GPIO_MUX_C,
154  .mosi_mux = GPIO_MUX_C,
155  .clk_mux = GPIO_MUX_C,
156  .miso_pad = SPI_PAD_MISO_2,
157  .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
158  .gclk_src = SAM0_GCLK_PERIPH,
159 #ifdef MODULE_PERIPH_DMA
160  .tx_trigger = SERCOM1_DMAC_ID_TX,
161  .rx_trigger = SERCOM1_DMAC_ID_RX,
162 #endif
163  },
164  { /* Connected to TFT display */
165  .dev = &(SERCOM4->SPI),
166  .miso_pin = GPIO_PIN(PB, 12),
167  .mosi_pin = GPIO_PIN(PB, 15),
168  .clk_pin = GPIO_PIN(PB, 13),
169  .miso_mux = GPIO_MUX_C,
170  .mosi_mux = GPIO_MUX_C,
171  .clk_mux = GPIO_MUX_C,
172  .miso_pad = SPI_PAD_MISO_0,
173  .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
174  .gclk_src = SAM0_GCLK_PERIPH,
175 #ifdef MODULE_PERIPH_DMA
176  .tx_trigger = SERCOM4_DMAC_ID_TX,
177  .rx_trigger = SERCOM4_DMAC_ID_RX,
178 #endif
179  },
180  { /* Connected to PDM Mic */
181  .dev = &(SERCOM3->SPI),
182  .miso_pin = GPIO_PIN(PA, 18),
183  .mosi_pin = GPIO_PIN(PA, 19),
184  .clk_pin = GPIO_PIN(PA, 16),
185  .miso_mux = GPIO_MUX_D,
186  .mosi_mux = GPIO_MUX_D,
187  .clk_mux = GPIO_MUX_D,
188  .miso_pad = SPI_PAD_MISO_2,
189  .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
190  .gclk_src = SAM0_GCLK_PERIPH,
191 #ifdef MODULE_PERIPH_DMA
192  .tx_trigger = SERCOM4_DMAC_ID_TX,
193  .rx_trigger = SERCOM4_DMAC_ID_RX,
194 #endif
195  },
196 #ifdef MODULE_PERIPH_SPI_ON_QSPI
197  { /* QSPI in SPI mode */
198  .dev = QSPI,
199  .miso_pin = SAM0_QSPI_PIN_DATA_1,
200  .mosi_pin = SAM0_QSPI_PIN_DATA_0,
201  .clk_pin = SAM0_QSPI_PIN_CLK,
202  .miso_mux = SAM0_QSPI_MUX,
203  .mosi_mux = SAM0_QSPI_MUX,
204  .clk_mux = SAM0_QSPI_MUX,
205  .miso_pad = SPI_PAD_MISO_0, /* unused */
206  .mosi_pad = SPI_PAD_MOSI_0_SCK_1, /* unused */
207  .gclk_src = SAM0_GCLK_MAIN, /* unused */
208 #ifdef MODULE_PERIPH_DMA
209  .tx_trigger = QSPI_DMAC_ID_TX,
210  .rx_trigger = QSPI_DMAC_ID_RX,
211 #endif
212  },
213 #endif
214 };
215 
216 #define SPI_NUMOF ARRAY_SIZE(spi_config)
223 static const i2c_conf_t i2c_config[] = {
224  {
225  .dev = &(SERCOM2->I2CM),
226  .speed = I2C_SPEED_NORMAL,
227  .scl_pin = GPIO_PIN(PA, 13),
228  .sda_pin = GPIO_PIN(PA, 12),
229  .mux = GPIO_MUX_C,
230  .gclk_src = SAM0_GCLK_PERIPH,
231  .flags = I2C_FLAG_NONE
232  },
233 };
234 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
241 #ifndef RTT_FREQUENCY
242 #define RTT_FREQUENCY (32768U)
243 #endif
250 static const sam0_common_usb_config_t sam_usbdev_config[] = {
251  {
252  .dm = GPIO_PIN(PA, 24),
253  .dp = GPIO_PIN(PA, 25),
254  .d_mux = GPIO_MUX_H,
255  .device = &USB->DEVICE,
256  .gclk_src = SAM0_GCLK_48MHZ,
257  }
258 };
266 /* ADC Default values */
267 #define ADC_GCLK_SRC SAM0_GCLK_PERIPH
268 #define ADC_PRESCALER ADC_CTRLA_PRESCALER_DIV8
269 
270 #define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG(0x18u)
271 #define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
272 
273 static const adc_conf_chan_t adc_channels[] = {
274  /* port, pin, muxpos, dev */
275  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA05, .dev = ADC0 }, /* A1 */
276  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB08, .dev = ADC0 }, /* A2 */
277  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB09, .dev = ADC0 }, /* A3 */
278  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA04, .dev = ADC0 }, /* A4 */
279  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA06, .dev = ADC0 }, /* A5 */
280  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PB01, .dev = ADC0 }, /* A6 - VMEAS */
281  { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB04, .dev = ADC1 }, /* A7 - Light sensor */
282 };
283 
284 #define ADC_NUMOF ARRAY_SIZE(adc_channels)
291 #define DAC_CLOCK SAM0_GCLK_TIMER
296 #define DAC_VREF DAC_CTRLB_REFSEL_VREFPU
299 #ifdef __cplusplus
300 }
301 #endif
302 
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
Definition: container.h:82
static const gpio_t adc_channels[]
Static array with declared ADC channels.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
@ UART_PAD_RX_1
select pad 1
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_2
use pad 2 for MISO line
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0
select pad 0
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_G
select peripheral function G
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_3_SCK_1
use pad 3 for MOSI, pad 1 for SCK
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition: periph_cpu.h:73
#define ADC0_INPUTCTRL_MUXPOS_PA04
Alias for AIN4.
Definition: periph_cpu.h:129
#define SAM0_QSPI_PIN_CLK
Clock
Definition: periph_cpu.h:268
#define ADC1_INPUTCTRL_MUXPOS_PB04
Alias for AIN6.
Definition: periph_cpu.h:148
#define ADC0_INPUTCTRL_MUXPOS_PA05
Alias for AIN5.
Definition: periph_cpu.h:130
#define ADC0_INPUTCTRL_MUXPOS_PB01
Alias for AIN13.
Definition: periph_cpu.h:138
#define SAM0_QSPI_PIN_DATA_0
D0 / MOSI
Definition: periph_cpu.h:270
#define SAM0_QSPI_PIN_DATA_1
D1 / MISO
Definition: periph_cpu.h:271
#define ADC0_INPUTCTRL_MUXPOS_PB08
Alias for AIN2.
Definition: periph_cpu.h:127
#define SAM0_QSPI_MUX
QSPI mux
Definition: periph_cpu.h:274
#define ADC0_INPUTCTRL_MUXPOS_PB09
Alias for AIN3.
Definition: periph_cpu.h:128
#define ADC0_INPUTCTRL_MUXPOS_PA06
Alias for AIN6.
Definition: periph_cpu.h:131
#define SAM0_GCLK_PERIPH
12-48 MHz (DFLL) clock
Definition: periph_cpu.h:81
@ SAM0_GCLK_TIMER
4/8MHz clock for timers
Definition: periph_cpu.h:70
@ SAM0_GCLK_48MHZ
48MHz clock
Definition: periph_cpu.h:72
ADC Channel Configuration.
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
PWM channel configuration data structure.
PWM device configuration.
tc_tcc_cfg_t tim
timer configuration
USB peripheral parameters.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218