periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  * Copyright (C) 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
10 #pragma once
11 
23 /* This board provides an LSE */
24 #ifndef CONFIG_BOARD_HAS_LSE
25 #define CONFIG_BOARD_HAS_LSE 1
26 #endif
27 
28 /* This board provides an HSE */
29 #ifndef CONFIG_BOARD_HAS_HSE
30 #define CONFIG_BOARD_HAS_HSE 1
31 #endif
32 
33 #include "periph_cpu.h"
34 #include "clk_conf.h"
35 #include "cfg_i2c1_pb8_pb9.h"
36 #include "cfg_timer_tim5.h"
37 #include "cfg_usb_otg_fs.h"
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
47 static const dma_conf_t dma_config[] = {
48  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
49  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
50 };
51 
52 #define DMA_0_ISR isr_dma2_stream3
53 #define DMA_1_ISR isr_dma2_stream2
54 
55 #define DMA_NUMOF ARRAY_SIZE(dma_config)
62 static const uart_conf_t uart_config[] = {
63  {
64  .dev = USART3,
65  .rcc_mask = RCC_APB1ENR_USART3EN,
66  .rx_pin = GPIO_PIN(PORT_D, 9),
67  .tx_pin = GPIO_PIN(PORT_D, 8),
68  .rx_af = GPIO_AF7,
69  .tx_af = GPIO_AF7,
70  .bus = APB1,
71  .irqn = USART3_IRQn,
72 #ifdef MODULE_PERIPH_DMA
73  .dma = DMA_STREAM_UNDEF,
74  .dma_chan = UINT8_MAX,
75 #endif
76  },
77  {
78  .dev = USART6,
79  .rcc_mask = RCC_APB2ENR_USART6EN,
80  .rx_pin = GPIO_PIN(PORT_G, 9),
81  .tx_pin = GPIO_PIN(PORT_G, 14),
82  .rx_af = GPIO_AF8,
83  .tx_af = GPIO_AF8,
84  .bus = APB2,
85  .irqn = USART6_IRQn,
86 #ifdef MODULE_PERIPH_DMA
87  .dma = DMA_STREAM_UNDEF,
88  .dma_chan = UINT8_MAX,
89 #endif
90  },
91  {
92  .dev = USART2,
93  .rcc_mask = RCC_APB2ENR_USART1EN,
94  .rx_pin = GPIO_PIN(PORT_D, 6),
95  .tx_pin = GPIO_PIN(PORT_D, 5),
96  .rx_af = GPIO_AF7,
97  .tx_af = GPIO_AF7,
98  .bus = APB2,
99  .irqn = USART2_IRQn,
100 #ifdef MODULE_PERIPH_DMA
101  .dma = DMA_STREAM_UNDEF,
102  .dma_chan = UINT8_MAX,
103 #endif
104  },
105 };
106 
107 #define UART_0_ISR (isr_usart3)
108 #define UART_1_ISR (isr_usart6)
109 #define UART_2_ISR (isr_usart2)
110 
111 #define UART_NUMOF ARRAY_SIZE(uart_config)
118 static const pwm_conf_t pwm_config[] = {
119  {
120  .dev = TIM1,
121  .rcc_mask = RCC_APB2ENR_TIM1EN,
122  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
123  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
124  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
125  { .pin = GPIO_UNDEF, .cc_chan = 0} },
126  .af = GPIO_AF1,
127  .bus = APB2
128  },
129  {
130  .dev = TIM4,
131  .rcc_mask = RCC_APB1ENR_TIM4EN,
132  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
133  { .pin = GPIO_UNDEF, .cc_chan = 0},
134  { .pin = GPIO_UNDEF, .cc_chan = 0},
135  { .pin = GPIO_UNDEF, .cc_chan = 0} },
136  .af = GPIO_AF2,
137  .bus = APB1
138  },
139 };
140 
141 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
148 static const spi_conf_t spi_config[] = {
149  {
150  .dev = SPI1,
151  .mosi_pin = GPIO_PIN(PORT_A, 7),
152  .miso_pin = GPIO_PIN(PORT_A, 6),
153  .sclk_pin = GPIO_PIN(PORT_A, 5),
154  .cs_pin = GPIO_PIN(PORT_A, 4),
155  .mosi_af = GPIO_AF5,
156  .miso_af = GPIO_AF5,
157  .sclk_af = GPIO_AF5,
158  .cs_af = GPIO_AF5,
159  .rccmask = RCC_APB2ENR_SPI1EN,
160  .apbbus = APB2,
161 #ifdef MODULE_PERIPH_DMA
162  .tx_dma = 0,
163  .tx_dma_chan = 3,
164  .rx_dma = 1,
165  .rx_dma_chan = 3,
166 #endif
167  }
168 };
169 
170 #define SPI_NUMOF ARRAY_SIZE(spi_config)
183 static const adc_conf_t adc_config[] = {
184  {GPIO_PIN(PORT_A, 3), 0, 3},
185  {GPIO_PIN(PORT_C, 0), 0, 10},
186  {GPIO_PIN(PORT_C, 3), 0, 13},
187  {GPIO_PIN(PORT_C, 1), 0, 11},
188  {GPIO_PIN(PORT_C, 4), 0, 14},
189  {GPIO_PIN(PORT_C, 5), 0, 15},
190  {GPIO_UNDEF, 0, 18}, /* VBAT */
191 };
192 
193 #define VBAT_ADC ADC_LINE(6)
194 #define ADC_NUMOF ARRAY_SIZE(adc_config)
197 #ifdef __cplusplus
198 }
199 #endif
200 
@ PORT_G
port G
Definition: periph_cpu.h:52
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
@ PORT_D
port D
Definition: periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:110
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218