periph_conf.h

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/*
 * Copyright (C) 2020 Inria
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#pragma once
 
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE            1
#endif
 
#include "periph_cpu.h"
#include "clk_conf.h"
#include "cfg_i2c1_pb6_pb7.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
static const uart_conf_t uart_config[] = {
    {
        .dev        = USART2,
        .rcc_mask   = RCC_APB1ENR_USART2EN,
        .rx_pin     = GPIO_PIN(PORT_A, 15),
        .tx_pin     = GPIO_PIN(PORT_A, 2),
        .rx_af      = GPIO_AF4,
        .tx_af      = GPIO_AF4,
        .bus        = APB1,
        .irqn       = USART2_IRQn,
        .type       = STM32_USART,
        .clk_src    = 0, /* Use APB clock */
    }
};
 
#define UART_0_ISR          (isr_usart2)
 
#define UART_NUMOF          ARRAY_SIZE(uart_config)
static const spi_conf_t spi_config[] = {
    {
        .dev      = SPI1,
        .mosi_pin = GPIO_PIN(PORT_B, 5),
        .miso_pin = GPIO_PIN(PORT_B, 4),
        .sclk_pin = GPIO_PIN(PORT_B, 3),
        .cs_pin   = SPI_CS_UNDEF,
        .mosi_af  = GPIO_AF0,
        .miso_af  = GPIO_AF0,
        .sclk_af  = GPIO_AF0,
        .cs_af    = GPIO_AF0,
        .rccmask  = RCC_APB2ENR_SPI1EN,
        .apbbus   = APB2
    }
};
 
#define SPI_NUMOF           ARRAY_SIZE(spi_config)
static const adc_conf_t adc_config[] = {
    { GPIO_PIN(PORT_A, 0), 0 },  /* Pin A0 */
    { GPIO_PIN(PORT_A, 1), 1 },  /* Pin A1 */
    { GPIO_PIN(PORT_A, 3), 3 },  /* Pin A2 */
    { GPIO_PIN(PORT_A, 4), 4 },  /* Pin A3 */
    { GPIO_PIN(PORT_A, 5), 5 },  /* Pin A4 */
    { GPIO_PIN(PORT_A, 6), 6 },  /* Pin A5 */
    { GPIO_PIN(PORT_A, 7), 7 },  /* Pin A6 */
};
 
#define ADC_NUMOF           ARRAY_SIZE(adc_config)
#ifdef __cplusplus
}
#endif