periph_conf.h
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1 /*
2  * Copyright (C) 2017 Freie Universität Berlin
3  * 2017 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
10 #pragma once
11 
23 /* Add specific clock configuration (HSE, LSE) for this board here */
24 #ifndef CONFIG_BOARD_HAS_LSE
25 #define CONFIG_BOARD_HAS_LSE 1
26 #endif
27 
28 #include "periph_cpu.h"
29 #include "clk_conf.h"
30 #include "cfg_rtt_default.h"
31 #include "cfg_timer_tim2.h"
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
41 static const uart_conf_t uart_config[] = {
42  {
43  .dev = USART2,
44  .rcc_mask = RCC_APB1ENR_USART2EN,
45  .rx_pin = GPIO_PIN(PORT_A, 3),
46  .tx_pin = GPIO_PIN(PORT_A, 2),
47  .rx_af = GPIO_AF4,
48  .tx_af = GPIO_AF4,
49  .bus = APB1,
50  .irqn = USART2_IRQn,
51  .type = STM32_USART,
52  .clk_src = 0, /* Use APB clock */
53  },
54  {
55  .dev = USART1,
56  .rcc_mask = RCC_APB2ENR_USART1EN,
57  .rx_pin = GPIO_PIN(PORT_A, 10),
58  .tx_pin = GPIO_PIN(PORT_A, 9),
59  .rx_af = GPIO_AF4,
60  .tx_af = GPIO_AF4,
61  .bus = APB2,
62  .irqn = USART1_IRQn,
63  .type = STM32_USART,
64  .clk_src = 0, /* Use APB clock */
65  },
66 #ifdef MODULE_PERIPH_LPUART
67  {
68  .dev = LPUART1,
69  .rcc_mask = RCC_APB1ENR_LPUART1EN,
70  .rx_pin = GPIO_PIN(PORT_C, 11),
71  .tx_pin = GPIO_PIN(PORT_C, 10),
72  .rx_af = GPIO_AF0,
73  .tx_af = GPIO_AF0,
74  .bus = APB1,
75  .irqn = LPUART1_IRQn,
76  .type = STM32_LPUART,
77  .clk_src = 0, /* Use APB clock */
78  },
79 #endif
80 };
81 
82 #define UART_0_ISR (isr_usart2)
83 #define UART_1_ISR (isr_usart1)
84 
85 #ifdef MODULE_PERIPH_LPUART
86 #define UART_2_ISR (isr_rng_lpuart1)
87 #endif
88 
89 #define UART_NUMOF ARRAY_SIZE(uart_config)
96 static const pwm_conf_t pwm_config[] = {
97  {
98  .dev = TIM3,
99  .rcc_mask = RCC_APB1ENR_TIM3EN,
100  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
101  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
102  { .pin = GPIO_PIN(PORT_C, 8) , .cc_chan = 2 },
103  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
104  .af = GPIO_AF2,
105  .bus = APB1
106  }
107 };
108 
109 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
116 static const spi_conf_t spi_config[] = {
117  {
118  .dev = SPI1,
119  .mosi_pin = GPIO_PIN(PORT_A, 7),
120  .miso_pin = GPIO_PIN(PORT_A, 6),
121  .sclk_pin = GPIO_PIN(PORT_A, 5),
122  .cs_pin = SPI_CS_UNDEF,
123  .mosi_af = GPIO_AF0,
124  .miso_af = GPIO_AF0,
125  .sclk_af = GPIO_AF0,
126  .cs_af = GPIO_AF0,
127  .rccmask = RCC_APB2ENR_SPI1EN,
128  .apbbus = APB2
129  }
130 };
131 
132 #define SPI_NUMOF ARRAY_SIZE(spi_config)
139 static const adc_conf_t adc_config[] = {
140  { GPIO_PIN(PORT_A, 0), 0 },
141  { GPIO_PIN(PORT_A, 1), 1 },
142  { GPIO_PIN(PORT_A, 4), 4 },
143  { GPIO_PIN(PORT_B, 0), 8 },
144  { GPIO_PIN(PORT_C, 1), 11 },
145  { GPIO_PIN(PORT_C, 0), 10 }
146 };
147 
148 #define ADC_NUMOF ARRAY_SIZE(adc_config)
155 static const i2c_conf_t i2c_config[] = {
156  {
157  .dev = I2C1,
158  .speed = I2C_SPEED_NORMAL,
159  .scl_pin = GPIO_PIN(PORT_B, 8),
160  .sda_pin = GPIO_PIN(PORT_B, 9),
161  .scl_af = GPIO_AF4,
162  .sda_af = GPIO_AF4,
163  .bus = APB1,
164  .rcc_mask = RCC_APB1ENR_I2C1EN,
165  .irqn = I2C1_IRQn
166  },
167  {
168  .dev = I2C2,
169  .speed = I2C_SPEED_NORMAL,
170  .scl_pin = GPIO_PIN(PORT_B, 13),
171  .sda_pin = GPIO_PIN(PORT_B, 14),
172  .scl_af = GPIO_AF5,
173  .sda_af = GPIO_AF5,
174  .bus = APB1,
175  .rcc_mask = RCC_APB1ENR_I2C2EN,
176  .irqn = I2C2_IRQn
177  }
178 };
179 
180 #define I2C_0_ISR isr_i2c1
181 #define I2C_1_ISR isr_i2c2
182 
183 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
186 #ifdef __cplusplus
187 }
188 #endif
189 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF0
use alternate function 0
Definition: cpu_gpio.h:101
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition: cpu_uart.h:38
@ STM32_USART
STM32 USART module type.
Definition: cpu_uart.h:37
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
ADC device configuration.
Definition: periph_cpu.h:377
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218