periph_conf.h
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1 /*
2  * Copyright (C) 2016 Fundacion Inria Chile
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
9 #pragma once
10 
21 #include "periph_cpu.h"
22 #include "clk_conf.h"
23 #include "cfg_timer_tim5.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 static const uart_conf_t uart_config[] = {
34  {
35  .dev = USART3,
36  .rcc_mask = RCC_APB1ENR_USART3EN,
37  .rx_pin = GPIO_PIN(PORT_B, 11),
38  .tx_pin = GPIO_PIN(PORT_B, 10),
39  .rx_af = GPIO_AF7,
40  .tx_af = GPIO_AF7,
41  .bus = APB1,
42  .irqn = USART3_IRQn
43  },
44  {
45  .dev = USART2,
46  .rcc_mask = RCC_APB1ENR_USART2EN,
47  .rx_pin = GPIO_PIN(PORT_A, 3),
48  .tx_pin = GPIO_PIN(PORT_A, 2),
49  .rx_af = GPIO_AF7,
50  .tx_af = GPIO_AF7,
51  .bus = APB1,
52  .irqn = USART2_IRQn
53  },
54  {
55  .dev = USART1,
56  .rcc_mask = RCC_APB2ENR_USART1EN,
57  .rx_pin = GPIO_PIN(PORT_A, 10),
58  .tx_pin = GPIO_PIN(PORT_A, 9),
59  .rx_af = GPIO_AF7,
60  .tx_af = GPIO_AF7,
61  .bus = APB2,
62  .irqn = USART1_IRQn
63  }
64 };
65 
66 #define UART_0_ISR (isr_usart3)
67 #define UART_1_ISR (isr_usart2)
68 #define UART_2_ISR (isr_usart1)
69 
70 #define UART_NUMOF ARRAY_SIZE(uart_config)
77 static const pwm_conf_t pwm_config[] = {
78  {
79  .dev = TIM3,
80  .rcc_mask = RCC_APB1ENR_TIM3EN,
81  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
82  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
83  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
84  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
85  .af = GPIO_AF2,
86  .bus = APB1
87  }
88 };
89 
90 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
97 static const spi_conf_t spi_config[] = {
98  {
99  .dev = SPI1,
100  .mosi_pin = GPIO_PIN(PORT_B, 5),
101  .miso_pin = GPIO_PIN(PORT_B, 4),
102  .sclk_pin = GPIO_PIN(PORT_B, 3),
103  .cs_pin = SPI_CS_UNDEF,
104  .mosi_af = GPIO_AF5,
105  .miso_af = GPIO_AF5,
106  .sclk_af = GPIO_AF5,
107  .cs_af = GPIO_AF5,
108  .rccmask = RCC_APB2ENR_SPI1EN,
109  .apbbus = APB2
110  },
111  {
112  .dev = SPI2,
113  .mosi_pin = GPIO_PIN(PORT_B, 15),
114  .miso_pin = GPIO_PIN(PORT_B, 14),
115  .sclk_pin = GPIO_PIN(PORT_B, 13),
116  .cs_pin = SPI_CS_UNDEF,
117  .mosi_af = GPIO_AF5,
118  .miso_af = GPIO_AF5,
119  .sclk_af = GPIO_AF5,
120  .cs_af = GPIO_AF5,
121  .rccmask = RCC_APB1ENR_SPI2EN,
122  .apbbus = APB1
123  },
124  {
125  .dev = SPI3,
126  .mosi_pin = GPIO_PIN(PORT_C, 12),
127  .miso_pin = GPIO_PIN(PORT_C, 11),
128  .sclk_pin = GPIO_PIN(PORT_C, 10),
129  .cs_pin = SPI_CS_UNDEF,
130  .mosi_af = GPIO_AF6,
131  .miso_af = GPIO_AF6,
132  .sclk_af = GPIO_AF6,
133  .cs_af = GPIO_AF6,
134  .rccmask = RCC_APB1ENR_SPI3EN,
135  .apbbus = APB1
136  }
137 };
138 
139 #define SPI_NUMOF ARRAY_SIZE(spi_config)
146 static const i2c_conf_t i2c_config[] = {
147  {
148  .dev = I2C1,
149  .speed = I2C_SPEED_NORMAL,
150  .scl_pin = GPIO_PIN(PORT_B, 8),
151  .sda_pin = GPIO_PIN(PORT_B, 9),
152  .scl_af = GPIO_AF4,
153  .sda_af = GPIO_AF4,
154  .bus = APB1,
155  .rcc_mask = RCC_APB1ENR_I2C1EN,
156  .clk = CLOCK_APB1,
157  .irqn = I2C1_EV_IRQn
158  }
159 };
160 
161 #define I2C_0_ISR isr_i2c1_ev
162 
163 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
170 static const adc_conf_t adc_config[] = {
171  { GPIO_PIN(PORT_C, 0), 10 },
172  { GPIO_PIN(PORT_C, 1), 11 },
173  { GPIO_PIN(PORT_C, 2), 12 },
174  /* ADC Temperature channel */
175  { GPIO_UNDEF, 16 },
176  /* ADC VREF channel */
177  { GPIO_UNDEF, 17 },
178 };
179 
180 #define ADC_NUMOF ARRAY_SIZE(adc_config)
187 static const dac_conf_t dac_config[] = {
188  { .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
189  { .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
190 };
191 
192 #define DAC_NUMOF ARRAY_SIZE(dac_config)
195 #ifdef __cplusplus
196 }
197 #endif
198 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
static const dac_conf_t dac_config[]
DAC configuration.
Definition: periph_conf.h:252
Common configuration for STM32 Timer peripheral based on TIM5.
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF6
use alternate function 6
Definition: cpu_gpio.h:107
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
#define CLOCK_APB1
Half AHB clock.
ADC device configuration.
Definition: periph_cpu.h:377
DAC line configuration data.
Definition: periph_cpu.h:300
gpio_t pin
pin connected to the line
Definition: periph_cpu.h:301
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218