periph_conf.h
Go to the documentation of this file.
1 /*
2  * SPDX-FileCopyrightText: 2024 ML!PA Consulting GmbH
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
18 #include "periph_cpu.h"
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
28 #ifndef CLOCK_CORECLOCK
29 #define CLOCK_CORECLOCK MHZ(120)
30 #endif
37 #define EXTERNAL_OSC32_SOURCE 1
38 #define INTERNAL_OSC32_SOURCE 0
39 #define ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE 0
46 #define USE_VREG_BUCK (1)
47 
52 #define ADC_GCLK_SRC SAM0_GCLK_PERIPH
53 #define ADC_PRESCALER ADC_CTRLA_PRESCALER_DIV8
54 #define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG(0x18u)
55 #define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
56 
57 static const adc_conf_chan_t adc_channels[] = {
58  /* port, pin, muxpos, dev */
59  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA02, .dev = ADC0 }, /* A0 */
60  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA05, .dev = ADC0 }, /* A1 */
61  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA06, .dev = ADC0 }, /* A2 */
62  { .inputctrl = ADC0_INPUTCTRL_MUXPOS_PA04, .dev = ADC0 }, /* A3 */
63  { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB08, .dev = ADC1 }, /* A4 */
64  { .inputctrl = ADC1_INPUTCTRL_MUXPOS_PB09, .dev = ADC1 }, /* A5 */
65 };
66 
67 #define ADC_NUMOF ARRAY_SIZE(adc_channels)
74  /* Must not exceed 12 MHz */
75 #define DAC_CLOCK SAM0_GCLK_TIMER
76  /* Use external reference voltage on PA03 */
77  /* (A solder jumper connects PA03 to 3V3 on the
78  * back of the board. We assume the jumper has
79  * not been cut.) */
80 #define DAC_VREF DAC_CTRLB_REFSEL_VREFPU
87 static const i2c_conf_t i2c_config[] = {
88  {
89  .dev = &(SERCOM5->I2CM),
90  .speed = I2C_SPEED_NORMAL,
91  .scl_pin = GPIO_PIN(PB, 3), /* D: SERCOM5.1 */
92  .sda_pin = GPIO_PIN(PB, 2), /* D: SERCOM5.0 */
93  .mux = GPIO_MUX_D,
94  .gclk_src = SAM0_GCLK_PERIPH,
95  .flags = I2C_FLAG_NONE
96  },
97 };
98 
99 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
106 #ifndef RTT_FREQUENCY
107 #define RTT_FREQUENCY (32768U)
108 #endif
115 static const tc32_conf_t timer_config[] = {
116  { /* Timer 0 - System Clock */
117  .dev = TC0,
118  .irq = TC0_IRQn,
119  .mclk = &MCLK->APBAMASK.reg,
120  .mclk_mask = MCLK_APBAMASK_TC0 | MCLK_APBAMASK_TC1,
121  .gclk_id = TC0_GCLK_ID,
122  .gclk_src = SAM0_GCLK_TIMER,
123  .flags = TC_CTRLA_MODE_COUNT32,
124  },
125  { /* Timer 1 */
126  .dev = TC2,
127  .irq = TC2_IRQn,
128  .mclk = &MCLK->APBBMASK.reg,
129  .mclk_mask = MCLK_APBBMASK_TC2 | MCLK_APBBMASK_TC3,
130  .gclk_id = TC2_GCLK_ID,
131  .gclk_src = SAM0_GCLK_TIMER,
132  .flags = TC_CTRLA_MODE_COUNT32,
133  }
134 };
135 
136 /* Timer 0 configuration */
137 #define TIMER_0_CHANNELS 2
138 #define TIMER_0_ISR isr_tc0
139 
140 /* Timer 1 configuration */
141 #define TIMER_1_CHANNELS 2
142 #define TIMER_1_ISR isr_tc2
143 
144 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
151 static const spi_conf_t spi_config[] = {
152  { /* SPI on ISP */
153  .dev = &(SERCOM2->SPI),
154  .miso_pin = GPIO_PIN(PA, 14), /* C: SERCOM2.2, D: SERCOM4.2 */
155  .mosi_pin = GPIO_PIN(PA, 12), /* C: SERCOM2.0, D: SERCOM4.1 */
156  .clk_pin = GPIO_PIN(PA, 13), /* C: SERCOM2.1, D: SERCOM4.0 */
157  .miso_mux = GPIO_MUX_C,
158  .mosi_mux = GPIO_MUX_C,
159  .clk_mux = GPIO_MUX_C,
160  .miso_pad = SPI_PAD_MISO_2,
161  .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
162  .gclk_src = SAM0_GCLK_PERIPH,
163 #if MODULE_PERIPH_DMA
164  .tx_trigger = SERCOM2_DMAC_ID_TX,
165  .rx_trigger = SERCOM2_DMAC_ID_RX,
166 #endif
167  },
168 #if !MODULE_PERIPH_UART
169  { /* D11=MOSI, D12=MISO, D13=SCK */
170  .dev = &(SERCOM3->SPI),
171  .miso_pin = GPIO_PIN(PA, 17), /* C: SERCOM1.1, D: SERCOM3.0 */
172  .mosi_pin = GPIO_PIN(PA, 19), /* C: SERCOM1.3, D: SERCOM3.3 */
173  .clk_pin = GPIO_PIN(PA, 16), /* C: SERCOM1.0, D: SERCOM3.1 */
174  .miso_mux = GPIO_MUX_D,
175  .mosi_mux = GPIO_MUX_D,
176  .clk_mux = GPIO_MUX_D,
177  .miso_pad = SPI_PAD_MISO_0,
178  .mosi_pad = SPI_PAD_MOSI_3_SCK_1,
179  .gclk_src = SAM0_GCLK_PERIPH,
180 # if MODULE_PERIPH_DMA
181  .tx_trigger = SERCOM3_DMAC_ID_TX,
182  .rx_trigger = SERCOM3_DMAC_ID_RX,
183 # endif
184  },
185 #endif
186 #if MODULE_PERIPH_SPI_ON_QSPI
187  { /* QSPI in SPI mode */
188  .dev = QSPI,
189  .miso_pin = SAM0_QSPI_PIN_DATA_1,
190  .mosi_pin = SAM0_QSPI_PIN_DATA_0,
191  .clk_pin = SAM0_QSPI_PIN_CLK,
192  .miso_mux = SAM0_QSPI_MUX,
193  .mosi_mux = SAM0_QSPI_MUX,
194  .clk_mux = SAM0_QSPI_MUX,
195  .miso_pad = SPI_PAD_MISO_0, /* unused */
196  .mosi_pad = SPI_PAD_MOSI_0_SCK_1, /* unused */
197  .gclk_src = SAM0_GCLK_MAIN, /* unused */
198 # if MODULE_PERIPH_DMA
199  .tx_trigger = QSPI_DMAC_ID_TX,
200  .rx_trigger = QSPI_DMAC_ID_RX,
201 # endif
202  },
203 #endif
204 };
205 
206 #define SPI_NUMOF ARRAY_SIZE(spi_config)
213 static const sam0_common_usb_config_t sam_usbdev_config[] = {
214  {
215  .dm = GPIO_PIN(PA, 24),
216  .dp = GPIO_PIN(PA, 25),
217  .d_mux = GPIO_MUX_H,
218  .device = &USB->DEVICE,
219  .gclk_src = SAM0_GCLK_PERIPH,
220  }
221 };
228 static const uart_conf_t uart_config[] = {
229 /* The UART pins can be routed to SERCOM3 (used by SPI) or
230  * SERCOM5 (used by I2C). The pad configuration for SERCOM5
231  * is impossible, as TXD cannot be routed to pad 1.
232  * Hence, we let periph_spi and periph_uart conflict in
233  * Makefile.features.
234  */
235  /* D0 = RXD, D1 = TXD */
236  {
237  .dev = &SERCOM3->USART,
238  .rx_pin = GPIO_PIN(PA, 23), /* C: SERCOM3.1, D: SERCOM5.0 */
239  .tx_pin = GPIO_PIN(PA, 22), /* C: SERCOM3.0, D: SERCOM5.1 */
240  #ifdef MODULE_PERIPH_UART_HW_FC
241  .rts_pin = GPIO_UNDEF,
242  .cts_pin = GPIO_UNDEF,
243  #endif
244  .mux = GPIO_MUX_C,
245  .rx_pad = UART_PAD_RX_1,
246  .tx_pad = UART_PAD_TX_0,
247  .flags = UART_FLAG_NONE,
248  .gclk_src = SAM0_GCLK_PERIPH,
249  },
250 };
251 
252 /* interrupt function name mapping */
253 #define UART_0_ISR isr_sercom3_2
254 #define UART_0_ISR_TX isr_sercom3_0
255 
256 #define UART_NUMOF ARRAY_SIZE(uart_config)
259 #ifdef __cplusplus
260 }
261 #endif
262 
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:65
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:36
static const gpio_t adc_channels[]
Static array with declared ADC channels.
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
@ UART_PAD_RX_1
select pad 1
@ PB
port B
@ PA
port A
@ I2C_FLAG_NONE
No flags set.
@ SPI_PAD_MISO_2
use pad 2 for MISO line
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ UART_FLAG_NONE
No flags set.
@ UART_PAD_TX_0
select pad 0
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_C
select peripheral function C
@ SPI_PAD_MOSI_3_SCK_1
use pad 3 for MOSI, pad 1 for SCK
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
#define ADC1_INPUTCTRL_MUXPOS_PB09
Alias for AIN1.
Definition: periph_cpu.h:143
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition: periph_cpu.h:73
#define ADC0_INPUTCTRL_MUXPOS_PA04
Alias for AIN4.
Definition: periph_cpu.h:129
#define ADC1_INPUTCTRL_MUXPOS_PB08
Alias for AIN0.
Definition: periph_cpu.h:142
#define SAM0_QSPI_PIN_CLK
Clock
Definition: periph_cpu.h:268
#define ADC0_INPUTCTRL_MUXPOS_PA05
Alias for AIN5.
Definition: periph_cpu.h:130
#define SAM0_QSPI_PIN_DATA_0
D0 / MOSI
Definition: periph_cpu.h:270
#define SAM0_QSPI_PIN_DATA_1
D1 / MISO
Definition: periph_cpu.h:271
#define SAM0_QSPI_MUX
QSPI mux
Definition: periph_cpu.h:274
#define ADC0_INPUTCTRL_MUXPOS_PA06
Alias for AIN6.
Definition: periph_cpu.h:131
#define ADC0_INPUTCTRL_MUXPOS_PA02
ADC pin aliases.
Definition: periph_cpu.h:125
#define SAM0_GCLK_PERIPH
12-48 MHz (DFLL) clock
Definition: periph_cpu.h:81
@ SAM0_GCLK_TIMER
4/8MHz clock for timers
Definition: periph_cpu.h:70
ADC Channel Configuration.
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
USB peripheral parameters.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218