cfg_i2c1_pb8_pb9.h
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1 /*
2  * SPDX-FileCopyrightText: 2018 Inria
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
18 #include "periph_cpu.h"
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
28 static const i2c_conf_t i2c_config[] = {
29  {
30  .dev = I2C1,
31  .speed = I2C_SPEED_NORMAL,
32  .scl_pin = GPIO_PIN(PORT_B, 8),
33  .sda_pin = GPIO_PIN(PORT_B, 9),
34 #if CPU_FAM_STM32F0
35  .scl_af = GPIO_AF1,
36  .sda_af = GPIO_AF1,
37 #elif CPU_FAM_STM32G0 || CPU_FAM_STM32C0
38  .scl_af = GPIO_AF6,
39  .sda_af = GPIO_AF6,
40 #else
41  .scl_af = GPIO_AF4,
42  .sda_af = GPIO_AF4,
43 #endif
44  .bus = APB1,
45 #if CPU_FAM_STM32F4 || CPU_FAM_STM32F2
46  .rcc_mask = RCC_APB1ENR_I2C1EN,
47  .clk = CLOCK_APB1,
48  .irqn = I2C1_EV_IRQn,
49 #elif CPU_FAM_STM32L4 || CPU_FAM_STM32WB || CPU_FAM_STM32G4
50  .rcc_mask = RCC_APB1ENR1_I2C1EN,
51  .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
52  .irqn = I2C1_ER_IRQn,
53 #elif CPU_FAM_STM32L5
54  .rcc_mask = RCC_APB1ENR1_I2C1EN,
55  .rcc_sw_mask = RCC_CCIPR1_I2C1SEL_1, /* HSI (16 MHz) */
56  .irqn = I2C1_ER_IRQn,
57 #elif CPU_FAM_STM32G0 || CPU_FAM_STM32C0
58  .rcc_mask = RCC_APBENR1_I2C1EN,
59  .rcc_sw_mask = RCC_CCIPR_I2C1SEL_1, /* HSI (16 MHz) */
60  .irqn = I2C1_IRQn,
61 #elif CPU_FAM_STM32F7
62  .rcc_mask = RCC_APB1ENR_I2C1EN,
63  .rcc_sw_mask = RCC_DCKCFGR2_I2C1SEL_1, /* HSI (16 MHz) */
64  .irqn = I2C1_ER_IRQn,
65 #elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0
66  .rcc_mask = RCC_APB1ENR_I2C1EN,
67 #if CPU_FAM_STM32F0
68  .rcc_sw_mask = RCC_CFGR3_I2C1SW,
69 #endif
70  .irqn = I2C1_IRQn,
71 #endif
72  }
73 };
74 
75 #if CPU_FAM_STM32F4 || CPU_FAM_STM32F2
76 #define I2C_0_ISR isr_i2c1_ev
77 #elif CPU_FAM_STM32L4 || CPU_FAM_STM32F7 || CPU_FAM_STM32WB || CPU_FAM_STM32L5
78 #define I2C_0_ISR isr_i2c1_er
79 #elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0 || CPU_FAM_STM32G0 || CPU_FAM_STM32C0
80 #define I2C_0_ISR isr_i2c1
81 #endif
82 
83 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
86 #ifdef __cplusplus
87 }
88 #endif
89 
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:47
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
GPIO_AF1
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
GPIO_AF4
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
GPIO_AF6
@ GPIO_AF6
use alternate function 6
Definition: cpu_gpio.h:107
APB1
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
I2C_SPEED_NORMAL
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
CLOCK_APB1
#define CLOCK_APB1
Half AHB clock.
Definition: periph_common_conf.h:37
i2c_conf_t
I2C configuration structure.
Definition: periph_cpu.h:298
i2c_conf_t::dev
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299