cfg_timer_tim2_tim15_tim16.h
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1 /*
2  * SPDX-FileCopyrightText: 2023 Otto-von-Guericke-Universität Magdeburg
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
19 #include "periph_cpu.h"
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
25 /* Please note: This likely needs some generalization for use in STM32 families
26  * other than L4. */
31 static const timer_conf_t timer_config[] = {
32  {
33  .dev = TIM2,
34  .max = 0xffffffff,
35 #if defined(RCC_APB1ENR_TIM2EN)
36  .rcc_mask = RCC_APB1ENR_TIM2EN,
37 #else
38  .rcc_mask = RCC_APB1ENR1_TIM2EN,
39 #endif
40  .bus = APB1,
41  .irqn = TIM2_IRQn
42  },
43  {
44  .dev = TIM15,
45  .max = 0x0000ffff,
46  .rcc_mask = RCC_APB2ENR_TIM15EN,
47  .bus = APB2,
48  .irqn = TIM1_BRK_TIM15_IRQn,
49  .channel_numof = 2,
50  },
51  {
52  .dev = TIM16,
53  .max = 0x0000ffff,
54  .rcc_mask = RCC_APB2ENR_TIM16EN,
55  .bus = APB2,
56  .irqn = TIM1_UP_TIM16_IRQn,
57  .channel_numof = 1,
58  },
59 };
60 
61 #define TIMER_0_ISR isr_tim2
62 #define TIMER_1_ISR isr_tim1_brk_tim15
63 #define TIMER_2_ISR isr_tim1_up_tim16
65 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
68 #ifdef __cplusplus
69 }
70 #endif
71 
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264