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irq_arch.h
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/*
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* Copyright (C) 2018 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#pragma once
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#include "
irq_arch_common.h
"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* On Xtensa-based ESP32x SoCs, interrupt 0 is reserved for the WiFi interface
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* and interrupt 1 is available. However, since interrupt 0 is not available on
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* RISC-V-based ESP32x SoCs, interrupt 1 is used for the WiFi interface instead.
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* Therefore, we use interrupt 1 for the RMT peripheral on Xtensa-based ESP32x
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* SoCs, but we use interrupt 11 for the RMT peripheral on RISC-V-based ESP32x
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* SoCs. Interrupt 11 is reserved for profiling on Xtensa-based ESP32x SoCs. */
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#if defined(__XTENSA__)
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# define CPU_INUM_RMT 1
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#else
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# define CPU_INUM_RMT 11
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#endif
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#define CPU_INUM_GPIO 2
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#define CPU_INUM_BLE 5
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#define CPU_INUM_RTT 9
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#define CPU_INUM_SERIAL_JTAG 10
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#define CPU_INUM_I2C 12
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#define CPU_INUM_UART 13
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#define CPU_INUM_CAN 17
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#define CPU_INUM_ETH 18
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#define CPU_INUM_USB 18
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#define CPU_INUM_LCDCAM 19
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#define CPU_INUM_FRC2 20
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#define CPU_INUM_SYSTIMER 20
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#define CPU_INUM_SDMMC 21
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#define CPU_INUM_TIMER 22
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#define CPU_INUM_WDT 23
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#define CPU_INUM_SOFTWARE 29
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void
esp_irq_init
(
void
);
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#ifdef __cplusplus
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}
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#endif
esp_irq_init
void esp_irq_init(void)
Initialize architecture specific interrupt handling.
irq_arch_common.h
Implementation of the kernels irq interface.
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