cpu_conf.h
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1 /*
2  * Copyright (C) 2016 Freie Universität Berlin
3  * 2016 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
10 #pragma once
11 
23 #include <stdint.h>
24 #include "cpu_conf_common.h"
25 
26 #if defined(CPU_LINE_STM32F030x4)
27 #include "vendor/stm32f030x4.h"
28 #elif defined(CPU_LINE_STM32MP157Cxx)
29 #include "vendor/stm32mp157cxx_cm4.h"
30 #elif CPU_FAM_STM32F0
31 #include "stm32f0xx.h"
32 #include "irqs/f0/irqs.h"
33 #elif CPU_FAM_STM32F1
34 #include "stm32f1xx.h"
35 #include "irqs/f1/irqs.h"
36 #elif CPU_FAM_STM32F2
37 #include "stm32f2xx.h"
38 #include "irqs/f2/irqs.h"
39 #elif CPU_FAM_STM32F3
40 #include "stm32f3xx.h"
41 #include "irqs/f3/irqs.h"
42 #elif CPU_FAM_STM32F4
43 #include "stm32f4xx.h"
44 #include "irqs/f4/irqs.h"
45 #elif CPU_FAM_STM32F7
46 #include "stm32f7xx.h"
47 #include "irqs/f7/irqs.h"
48 #elif CPU_FAM_STM32G0
49 #include "stm32g0xx.h"
50 #include "irqs/g0/irqs.h"
51 #elif CPU_FAM_STM32C0
52 #include "stm32c0xx.h"
53 #include "irqs/c0/irqs.h"
54 #elif CPU_FAM_STM32G4
55 #include "stm32g4xx.h"
56 #include "irqs/g4/irqs.h"
57 #elif CPU_FAM_STM32L0
58 #include "stm32l0xx.h"
59 #include "irqs/l0/irqs.h"
60 #elif CPU_FAM_STM32L1
61 #include "stm32l1xx.h"
62 #include "irqs/l1/irqs.h"
63 #elif CPU_FAM_STM32L4
64 #include "stm32l4xx.h"
65 #include "irqs/l4/irqs.h"
66 #elif CPU_FAM_STM32L5
67 #include "stm32l5xx.h"
68 #include "irqs/l5/irqs.h"
69 #elif CPU_FAM_STM32U5
70 #include "stm32u5xx.h"
71 #include "irqs/u5/irqs.h"
72 #define NUM_HEAPS 3
73 #elif CPU_FAM_STM32WB
74 #include "stm32wbxx.h"
75 #include "irqs/wb/irqs.h"
76 #elif CPU_FAM_STM32WL
77 #include "stm32wlxx.h"
78 #include "irqs/wl/irqs.h"
79 #else
80 #error Not supported CPU family
81 #endif
82 
83 /* add unused backup RAM as extra heap */
84 #if !defined(NUM_HEAPS) && CPU_HAS_BACKUP_RAM
85 #define NUM_HEAPS 2
86 #endif
87 
88 #ifdef __cplusplus
89 extern "C" {
90 #endif
91 
100 #define CORTEXM_ISB_REQUIRED_AFTER_WFI 1
101 
106 #define CPU_DEFAULT_IRQ_PRIO (1U)
107 /* STM32MP1 family has no flah */
108 #if !defined(CPU_FAM_STM32MP1)
109 #define CPU_FLASH_BASE FLASH_BASE
110 #endif
111 
112 /* CPU_IRQ_NUMOF cannot be determined automatically from cmsis header */
113 #if defined(CPU_LINE_STM32F030x4)
114 #define CPU_IRQ_NUMOF (28U)
115 #elif defined(CPU_MODEL_STM32MP157CAC)
116 #define CPU_IRQ_NUMOF (150U)
117 #endif
124 #if defined(CPU_FAM_STM32U5)
125 #define FLASHPAGE_SIZE (8192U)
126 #elif defined(CPU_FAM_STM32WB)
127 #define FLASHPAGE_SIZE (4096U)
128 #elif defined(CPU_LINE_STM32F091xC) || defined(CPU_LINE_STM32F072xB) \
129  || defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
130  || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
131  || defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) \
132  || defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL) \
133  || defined(CPU_FAM_STM32C0)
134 #define FLASHPAGE_SIZE (2048U)
135 #elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
136  || defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \
137  || defined(CPU_LINE_STM32F030x4) || defined(CPU_LINE_STM32F103xB) \
138  || defined(CPU_LINE_STM32F031x6)
139 #define FLASHPAGE_SIZE (1024U)
140 #elif defined(CPU_FAM_STM32L1)
141 #define FLASHPAGE_SIZE (256U)
142 #elif defined(CPU_FAM_STM32L0)
143 #define FLASHPAGE_SIZE (128U)
144 #endif
145 
146 #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
147 #define FLASHPAGE_ERASE_STATE (0x00U)
148 #endif
149 
150 #ifdef FLASHPAGE_SIZE
151 #define FLASHPAGE_NUMOF (STM32_FLASHSIZE / FLASHPAGE_SIZE)
152 #endif
153 
154 #if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
155  defined(CPU_FAM_STM32F7)
156 #define PERIPH_FLASHPAGE_CUSTOM_PAGESIZES
157 #define PERIPH_FLASHPAGE_NEEDS_FLASHPAGE_ADDR
158 
170 #if (defined(FLASH_OPTCR_DB1M) && (STM32_FLASHSIZE >= (1024 * 1024)))
171 #define FLASHPAGE_DUAL_BANK 1
172 #else
173 #define FLASHPAGE_DUAL_BANK 0
174 #endif
175 
176 /* stm32f7 uses single bank with 32KB to 256KB sectors on a number of devices */
177 #if defined(CPU_FAM_STM32F7)
178 #if defined(CPU_LINE_STM32F745xx) || \
179  defined(CPU_LINE_STM32F746xx) || \
180  defined(CPU_LINE_STM32F750xx) || \
181  defined(CPU_LINE_STM32F756xx) || \
182  defined(CPU_LINE_STM32F765xx) || \
183  defined(CPU_LINE_STM32F767xx) || \
184  defined(CPU_LINE_STM32F769xx) || \
185  defined(CPU_LINE_STM32F777xx) || \
186  defined(CPU_LINE_STM32F779xx)
187 #define FLASHPAGE_MIN_SECTOR_SIZE (32 * 1024)
188 #elif defined(CPU_LINE_STM32F722xx) || \
189  defined(CPU_LINE_STM32F723xx) || \
190  defined(CPU_LINE_STM32F730xx) || \
191  defined(CPU_LINE_STM32F732xx) || \
192  defined(CPU_LINE_STM32F733xx)
193 #define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
194 #else
195 /* Intentionally error on an unknown line to prevent flashpage errors */
196 #error Unknown STM32F7 Line, unable to determine FLASHPAGE_MIN_SECTOR_SIZE
197 #endif
198 
199 #else /* CPU_FAM_STM32F7 */
200 #define FLASHPAGE_MIN_SECTOR_SIZE (16 * 1024)
201 #endif
202 
203 #if FLASHPAGE_DUAL_BANK
204 /* Number of "large" sectors + 4 for the small sectors that together equal a
205  * single large sector. Times two to account for the two banks */
206 #define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
207  (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 8)
208 #else
209 /* Number of "large" sectors + 4 for the small sectors that together equal a
210  * single large sector, eg: 1 MB = 7 * 128 KB sectors + 1 64 KB and 4 16 KB
211  * sectors */
212 #define FLASHPAGE_NUMOF ((STM32_FLASHSIZE / \
213  (8 * FLASHPAGE_MIN_SECTOR_SIZE)) + 4)
214 #endif
215 
216 #endif
217 
218 /* The minimum block size which can be written depends on the family.
219  * However, the erase block is always FLASHPAGE_SIZE.
220  */
221 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
222  defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
223  defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
224  defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
225 #define FLASHPAGE_WRITE_BLOCK_SIZE (8U)
226 typedef uint64_t stm32_flashpage_block_t;
227 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
228  defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
229  defined(CPU_FAM_STM32F7)
230 #define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
231 typedef uint32_t stm32_flashpage_block_t;
232 #else
233 #define FLASHPAGE_WRITE_BLOCK_SIZE (2U)
234 typedef uint16_t stm32_flashpage_block_t;
235 #endif
236 
237 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
238  defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
239  defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
240  defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
241 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (8U)
242 #else
243 /* Writing should be always 4 bytes aligned */
244 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
245 #endif
252 #ifdef SRAM_BB_BASE
253 #define CPU_HAS_BITBAND 1
254 #endif
257 #ifdef __cplusplus
258 }
259 #endif
260