cpu_conf_kinetis_w.h
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1 /*
2  * SPDX-FileCopyrightText: 2017 Eistec AB
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
20 #if defined(KINETIS_CORE_D)
21 /* Kinetis KW2xD */
22 #if defined(CPU_MODEL_MKW21D256VHA5) || \
23  defined(CPU_MODEL_MKW21D512VHA5)
24 #include "vendor/MKW21D5.h"
25 #elif defined(CPU_MODEL_MKW22D512VHA5)
26 #include "vendor/MKW22D5.h"
27 #elif defined(CPU_MODEL_MKW24D512VHA5)
28 #include "vendor/MKW24D5.h"
29 #endif
30 
34 #define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
40 #define KW2XDRF_PORT_DEV PORTB
41 #define KW2XDRF_PORT PORT_B
42 #define KW2XDRF_GPIO GPIOB
43 #define KW2XDRF_PORT_IRQn PORTB_IRQn
45 #define KW2XDRF_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
46 #define KW2XDRF_PIN_AF 2
47 #define KW2XDRF_PCS0_PIN 10
48 #define KW2XDRF_SCK_PIN 11
49 #define KW2XDRF_SOUT_PIN 16
50 #define KW2XDRF_SIN_PIN 17
51 #define KW2XDRF_RST_PIN 19
52 #define KW2XDRF_IRQ_PIN 3
53 #define KW2XDRF_CLK_CTRL_PORT PORT_C
54 #define KW2XDRF_CLK_CTRL_PORT_DEV PORTC
55 #define KW2XDRF_CLK_CTRL_GPIO GPIOC
56 #define KW2XDRF_CLK_CTRL_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
57 #define KW2XDRF_CLK_CTRL_PIN 0
60 #elif defined(KINETIS_CORE_Z)
61 /* Kinetis KWxxZ */
62 #if defined(CPU_MODEL_MKW21Z256VHT4) || \
63  defined(CPU_MODEL_MKW21Z512VHT4)
64 #include "vendor/MKW21Z4.h"
65 #elif defined(CPU_MODEL_MKW31Z256VHT4) || \
66  defined(CPU_MODEL_MKW31Z512CAT4) || \
67  defined(CPU_MODEL_MKW31Z512VHT4)
68 #include "vendor/MKW31Z4.h"
69 #elif defined(CPU_MODEL_MKW41Z256VHT4) || \
70  defined(CPU_MODEL_MKW41Z512CAT4) || \
71  defined(CPU_MODEL_MKW41Z512VHT4)
72 #include "vendor/MKW41Z4.h"
73 #endif
74 #endif /* KINETIS_CORE_x */
75 
80 #define FLASHPAGE_SIZE (2048U)
81 #define FLASHPAGE_NUMOF ((KINETIS_ROMSIZE * 1024) / FLASHPAGE_SIZE)
82 
83 /* The minimum block size which can be written is 4B. However, the erase
84  * block is always FLASHPAGE_SIZE.
85  */
86 #define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
87 /* Writing should be always 4 bytes aligned */
88 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
89 /* Section erase and programming must be 8 bytes aligned */
90 #define FLASHPAGE_BLOCK_SECTION_ALIGNMENT (8U)
93 #ifdef __cplusplus
94 extern "C"
95 {
96 #endif
97 
98 #ifdef __cplusplus
99 }
100 #endif
101