periph_conf.h
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1 /*
2  * Copyright (C) 2018 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
9 #pragma once
10 
21 #include "periph_cpu.h"
22 
23 #ifdef __cplusplus
24 extern "C"
25 {
26 #endif
27 
32 static const clock_config_t clock_config = {
33  /*
34  * This configuration results in the system running with the internal clock
35  * with the following clock frequencies:
36  * Core: 8 MHz
37  * Bus: 8 MHz
38  * Flash: 8 MHz
39  */
40  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(0),
41  /* unsure if this RTC load cap configuration is correct */
42  .rtc_clc = RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK,
43  /* Use the 32 kHz system oscillator output as ERCLK32K. */
44  .osc32ksel = SIM_SOPT1_OSC32KSEL(0),
45  .clock_flags =
46  KINETIS_CLOCK_RTCOSC_EN |
47  KINETIS_CLOCK_USE_FAST_IRC |
48  KINETIS_CLOCK_MCGIRCLK_EN | /* Used for LPUART clocking */
49  KINETIS_CLOCK_MCGIRCLK_STOP_EN |
50  0,
51  /* Using LIRC8M mode by default */
52  .default_mode = KINETIS_MCG_MODE_LIRC8M,
53  /* The crystal connected to EXTAL0 is 32.768 kHz */
54  .erc_range = KINETIS_MCG_ERC_RANGE_LOW,
55  .osc_clc = 0, /* no load cap configuration, rtc_clc overrides this value on KL43Z */
56  .fcrdiv = MCG_SC_FCRDIV(0), /* LIRC_DIV1 divide by 1 => 8 MHz */
57  .lirc_div2 = MCG_MC_LIRC_DIV2(0), /* LIRC_DIV2 divide by 1 => 8 MHz */
58 };
59 #define CLOCK_CORECLOCK ( 8000000ul)
60 #define CLOCK_MCGIRCLK ( 8000000ul)
61 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
68 #define PIT_NUMOF (1U)
69 #define PIT_CONFIG { \
70  { \
71  .prescaler_ch = 0, \
72  .count_ch = 1, \
73  }, \
74 }
75 #define LPTMR_NUMOF (1U)
76 #define LPTMR_CONFIG { \
77  { \
78  .dev = LPTMR0, \
79  .irqn = LPTMR0_IRQn, \
80  .src = 2, \
81  .base_freq = 32768u, \
82  }, \
83  }
84 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
85 
86 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
87 #define PIT_ISR_0 isr_pit1
88 #define LPTMR_ISR_0 isr_lptmr0
95 static const uart_conf_t uart_config[] = {
96  {
97  .dev = LPUART0,
98  .freq = CLOCK_MCGIRCLK,
99  .pin_rx = GPIO_PIN(PORT_A, 1),
100  .pin_tx = GPIO_PIN(PORT_A, 2),
101  .pcr_rx = PORT_PCR_MUX(2),
102  .pcr_tx = PORT_PCR_MUX(2),
103  .irqn = LPUART0_IRQn,
104  .scgc_addr = &SIM->SCGC5,
105  .scgc_bit = SIM_SCGC5_LPUART0_SHIFT,
106  .mode = UART_MODE_8N1,
107  .type = KINETIS_LPUART,
108  },
109 };
110 #define UART_NUMOF ARRAY_SIZE(uart_config)
111 #define LPUART_0_ISR isr_lpuart0
112 /* Use MCGIRCLK (internal reference 4 MHz clock) */
113 #define LPUART_0_SRC 3
120 static const adc_conf_t adc_config[] = {
121  /* dev, pin, channel */
122  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8, .avg = ADC_AVG_MAX }, /* Arduino A0 */
123  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9, .avg = ADC_AVG_MAX }, /* Arduino A1 */
124  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 2), .chan = 15, .avg = ADC_AVG_MAX }, /* Arduino A2 */
125  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 3), .chan = 4, .avg = ADC_AVG_MAX }, /* Arduino A3 */
126  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 11, .avg = ADC_AVG_MAX }, /* Arduino A4 */
127  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15, .avg = ADC_AVG_MAX }, /* Arduino A5 */
128 };
129 
130 #define ADC_NUMOF ARRAY_SIZE(adc_config)
131 /*
132  * KL43Z ADC reference settings:
133  * 0: VREFH/VREFL external pin pair
134  * 1: VDDA/VSSA supply pins
135  * 2-3: reserved
136  */
137 #define ADC_REF_SETTING 0
144 static const i2c_conf_t i2c_config[] = {
145  {
146  .i2c = I2C0,
147  .scl_pin = GPIO_PIN(PORT_E, 24),
148  .sda_pin = GPIO_PIN(PORT_E, 25),
149  .freq = CLOCK_CORECLOCK,
150  .speed = I2C_SPEED_FAST,
151  .irqn = I2C0_IRQn,
152  .scl_pcr = (PORT_PCR_MUX(5)),
153  .sda_pcr = (PORT_PCR_MUX(5)),
154  },
155  {
156  .i2c = I2C1,
157  .scl_pin = GPIO_PIN(PORT_E, 1),
158  .sda_pin = GPIO_PIN(PORT_E, 0),
159  .freq = CLOCK_CORECLOCK,
160  .speed = I2C_SPEED_FAST,
161  .irqn = I2C1_IRQn,
162  .scl_pcr = (PORT_PCR_MUX(6)),
163  .sda_pcr = (PORT_PCR_MUX(6)),
164  },
165 };
166 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
167 #define I2C_0_ISR isr_i2c0
168 #define I2C_1_ISR isr_i2c1
171 #ifdef __cplusplus
172 }
173 #endif
174 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_E
port E
Definition: periph_cpu.h:50
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:250
#define CLOCK_CORECLOCK
System core clock in Hz.
Definition: periph_conf.h:34
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition: periph_cpu.h:278
@ KINETIS_LPUART
Kinetis Low-power UART (LPUART) module type.
Definition: periph_cpu.h:538
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition: periph_cpu.h:293
#define ADC_AVG_MAX
Maximum hardware averaging (32 samples)
Definition: periph_cpu.h:373
ADC device configuration.
Definition: periph_cpu.h:377
ADC_TypeDef * dev
ADC device used.
Definition: periph_cpu.h:378
I2C configuration structure.
Definition: periph_cpu.h:298
I2C_Type * i2c
Pointer to hardware module registers.
Definition: periph_cpu.h:458
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218