periph_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universität Berlin
3  * 2018 HAW Hamburg
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
10 #pragma once
11 
26 /*
27  * This board provides an LSE, so enable it before including the default clock config
28  */
29 #ifndef CONFIG_BOARD_HAS_LSE
30 #define CONFIG_BOARD_HAS_LSE 1
31 #endif
32 
33 #include "periph_cpu.h"
34 #include "clk_conf.h"
35 #include "cfg_timer_tim2.h"
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
45 static const uart_conf_t uart_config[] = {
46  {
47  .dev = USART1,
48  .rcc_mask = RCC_APB2ENR_USART1EN,
49  .rx_pin = GPIO_PIN(PORT_A, 10),
50  .tx_pin = GPIO_PIN(PORT_A, 9),
51  .rx_af = GPIO_AF7,
52  .tx_af = GPIO_AF7,
53  .bus = APB2,
54  .irqn = USART1_IRQn
55  },
56  {
57  .dev = USART2,
58  .rcc_mask = RCC_APB1ENR_USART2EN,
59  .rx_pin = GPIO_PIN(PORT_A, 3),
60  .tx_pin = GPIO_PIN(PORT_A, 2),
61  .rx_af = GPIO_AF7,
62  .tx_af = GPIO_AF7,
63  .bus = APB1,
64  .irqn = USART2_IRQn
65  }
66 };
67 
68 #define UART_0_ISR (isr_usart1)
69 #define UART_1_ISR (isr_usart2)
70 
71 #define UART_NUMOF ARRAY_SIZE(uart_config)
78 #define PWM_NUMOF 0
85 static const spi_conf_t spi_config[] = {
86  {
87  .dev = SPI1,
88  .mosi_pin = GPIO_PIN(PORT_A, 7),
89  .miso_pin = GPIO_PIN(PORT_A, 6),
90  .sclk_pin = GPIO_PIN(PORT_A, 5),
91  .cs_pin = GPIO_PIN(PORT_B, 0),
92  .mosi_af = GPIO_AF5,
93  .miso_af = GPIO_AF5,
94  .sclk_af = GPIO_AF5,
95  .cs_af = GPIO_AF5,
96  .rccmask = RCC_APB2ENR_SPI1EN,
97  .apbbus = APB2
98  },
99  {
100  .dev = SPI2,
101  .mosi_pin = GPIO_PIN(PORT_B, 14),
102  .miso_pin = GPIO_PIN(PORT_B, 15),
103  .sclk_pin = GPIO_PIN(PORT_B, 13),
104  .cs_pin = GPIO_PIN(PORT_B, 12),
105  .mosi_af = GPIO_AF5,
106  .miso_af = GPIO_AF5,
107  .sclk_af = GPIO_AF5,
108  .cs_af = GPIO_AF5,
109  .rccmask = RCC_APB1ENR_SPI2EN,
110  .apbbus = APB1
111  }
112 };
113 
114 #define SPI_NUMOF ARRAY_SIZE(spi_config)
121 static const i2c_conf_t i2c_config[] = {
122  {
123  .dev = I2C1,
124  .speed = I2C_SPEED_NORMAL,
125  .scl_pin = GPIO_PIN(PORT_B, 8),
126  .sda_pin = GPIO_PIN(PORT_B, 9),
127  .scl_af = GPIO_AF4,
128  .sda_af = GPIO_AF4,
129  .bus = APB1,
130  .rcc_mask = RCC_APB1ENR_I2C1EN,
131  .clk = CLOCK_APB1,
132  .irqn = I2C1_EV_IRQn
133  }
134 };
135 
136 #define I2C_0_ISR isr_i2c1_ev
137 
138 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
141 #ifdef __cplusplus
142 }
143 #endif
144 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:68
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:277
#define CLOCK_APB1
Half AHB clock.
I2C configuration structure.
Definition: periph_cpu.h:298
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:299
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218