30 #define CPUID_ADDR (&FCFG->MAC_BLE_0)
34 #define CPUID_LEN (16U)
40 #define PROVIDES_PM_SET_LOWEST_CORTEXM
47 #define HAVE_GPIO_MODE_T
60 #define HAVE_GPIO_FLANK_T
70 #define GPIO_PIN(x, y) (((x) & 0) | (y))
78 #define UART_INVALID_MODE (0x8000000)
84 #define HAVE_UART_PARITY_T
98 #define HAVE_UART_DATA_BITS_T
111 #define HAVE_UART_STOP_BITS_T
126 #ifdef MODULE_PERIPH_UART_HW_FC
155 #define TIMER_CHANNEL_NUMOF 2
157 #define PERIPH_I2C_NEED_READ_REG
158 #define PERIPH_I2C_NEED_READ_REGS
159 #define PERIPH_I2C_NEED_WRITE_REG
160 #define PERIPH_I2C_NEED_WRITE_REGS
@ GPIO_OUT
select GPIO MASK as output
@ GPIO_IN
select GPIO MASK as input
#define IOCFG_EDGEDET_BOTH
edge detection on both edges
#define IOCFG_IOMODE_OPEN_DRAIN
open drain
#define IOCFG_PULLCTL_DOWN
pull down
#define IOCFG_EDGEDET_RISING
edge detection on rising edge
#define IOCFG_PULLCTL_UP
pull up
#define IOCFG_PULLCTL_OFF
no IO pull
#define IOCFG_EDGEDET_FALLING
edge detection on falling edge
gpio_mode_t
Available pin modes.
@ GPIO_FALLING
emit interrupt on falling flank
@ GPIO_RISING
emit interrupt on rising flank
@ GPIO_BOTH
not supported -> random value
@ GPIO_OD
configure as output in open-drain mode without pull resistor
@ GPIO_IN_PU
configure as input with pull-up resistor
@ GPIO_OD_PU
configure as output in open-drain mode with pull resistor enabled
@ GPIO_IN_PD
configure as input with pull-down resistor
@ UART_PARITY_SPACE
space parity
@ UART_PARITY_NONE
no parity
@ UART_PARITY_EVEN
even parity
@ UART_PARITY_ODD
odd parity
@ UART_PARITY_MARK
mark parity
@ UART_STOP_BITS_2
2 stop bits
@ UART_STOP_BITS_1
1 stop bit
@ UART_DATA_BITS_6
6 data bits
@ UART_DATA_BITS_5
5 data bits
@ UART_DATA_BITS_7
7 data bits
@ UART_DATA_BITS_8
8 data bits
gpio_flank_t
Enumeration of supported GPIO flanks.
uart_parity_t
Definition of possible parity modes.
uart_stop_bits_t
Definition of possible stop bits lengths.
#define UART_INVALID_MODE
Invalid UART mode mask.
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Timer device configuration.
UART device configuration.
UART component registers.