cfg_clock_default_84.h
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1 /*
2  * Copyright (C) 2018 Freie Universität Berlin
3  * 2017 OTA keys S.A.
4  * 2018-2020 Inria
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
11 #pragma once
12 
25 #include "kernel_defines.h"
26 #include "macros/units.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 /* The following parameters configure a 84MHz system clock with HSE (8MHz, 16MHz
37  or 25MHz) or HSI (16MHz) as PLL input clock */
38 #ifndef CONFIG_CLOCK_PLL_M
39 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
40 #define CONFIG_CLOCK_PLL_M (25)
41 #else
42 #define CONFIG_CLOCK_PLL_M (4)
43 #endif
44 #endif
45 #ifndef CONFIG_CLOCK_PLL_N
46 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
47 #define CONFIG_CLOCK_PLL_N (168)
48 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
49 #define CONFIG_CLOCK_PLL_N (336)
50 #else
51 #define CONFIG_CLOCK_PLL_N (84)
52 #endif
53 #endif
54 #ifndef CONFIG_CLOCK_PLL_P
55 #define CONFIG_CLOCK_PLL_P (4)
56 #endif
57 #ifndef CONFIG_CLOCK_PLL_Q
58 #define CONFIG_CLOCK_PLL_Q (7)
59 #endif
60 #ifndef CONFIG_CLOCK_PLL_R
61 #define CONFIG_CLOCK_PLL_R (0)
62 #endif
69 #ifndef CONFIG_CLOCK_APB1_DIV
70 #define CONFIG_CLOCK_APB1_DIV (2) /* max 42MHz */
71 #endif
72 #ifndef CONFIG_CLOCK_APB2_DIV
73 #define CONFIG_CLOCK_APB2_DIV (1) /* max 84MHz */
74 #endif
77 #if CLOCK_CORECLOCK > MHZ(84)
78 #error "SYSCLK cannot exceed 84MHz"
79 #endif
80 
81 #ifdef __cplusplus
82 }
83 #endif
84 
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.
units.h
Unit helper macros.