cpu_conf_kinetis_w.h
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1 /*
2  * Copyright (C) 2017 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
9 #pragma once
10 
23 #if defined(KINETIS_CORE_D)
24 /* Kinetis KW2xD */
25 #if defined(CPU_MODEL_MKW21D256VHA5) || \
26  defined(CPU_MODEL_MKW21D512VHA5)
27 #include "vendor/MKW21D5.h"
28 #elif defined(CPU_MODEL_MKW22D512VHA5)
29 #include "vendor/MKW22D5.h"
30 #elif defined(CPU_MODEL_MKW24D512VHA5)
31 #include "vendor/MKW24D5.h"
32 #endif
33 
37 #define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
43 #define KW2XDRF_PORT_DEV PORTB
44 #define KW2XDRF_PORT PORT_B
45 #define KW2XDRF_GPIO GPIOB
46 #define KW2XDRF_PORT_IRQn PORTB_IRQn
48 #define KW2XDRF_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
49 #define KW2XDRF_PIN_AF 2
50 #define KW2XDRF_PCS0_PIN 10
51 #define KW2XDRF_SCK_PIN 11
52 #define KW2XDRF_SOUT_PIN 16
53 #define KW2XDRF_SIN_PIN 17
54 #define KW2XDRF_RST_PIN 19
55 #define KW2XDRF_IRQ_PIN 3
56 #define KW2XDRF_CLK_CTRL_PORT PORT_C
57 #define KW2XDRF_CLK_CTRL_PORT_DEV PORTC
58 #define KW2XDRF_CLK_CTRL_GPIO GPIOC
59 #define KW2XDRF_CLK_CTRL_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
60 #define KW2XDRF_CLK_CTRL_PIN 0
63 #elif defined(KINETIS_CORE_Z)
64 /* Kinetis KWxxZ */
65 #if defined(CPU_MODEL_MKW21Z256VHT4) || \
66  defined(CPU_MODEL_MKW21Z512VHT4)
67 #include "vendor/MKW21Z4.h"
68 #elif defined(CPU_MODEL_MKW31Z256VHT4) || \
69  defined(CPU_MODEL_MKW31Z512CAT4) || \
70  defined(CPU_MODEL_MKW31Z512VHT4)
71 #include "vendor/MKW31Z4.h"
72 #elif defined(CPU_MODEL_MKW41Z256VHT4) || \
73  defined(CPU_MODEL_MKW41Z512CAT4) || \
74  defined(CPU_MODEL_MKW41Z512VHT4)
75 #include "vendor/MKW41Z4.h"
76 #endif
77 #endif /* KINETIS_CORE_x */
78 
83 #define FLASHPAGE_SIZE (2048U)
84 #define FLASHPAGE_NUMOF ((KINETIS_ROMSIZE * 1024) / FLASHPAGE_SIZE)
85 
86 /* The minimum block size which can be written is 4B. However, the erase
87  * block is always FLASHPAGE_SIZE.
88  */
89 #define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
90 /* Writing should be always 4 bytes aligned */
91 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
92 /* Section erase and programming must be 8 bytes aligned */
93 #define FLASHPAGE_BLOCK_SECTION_ALIGNMENT (8U)
96 #ifdef __cplusplus
97 extern "C"
98 {
99 #endif
100 
101 #ifdef __cplusplus
102 }
103 #endif
104