periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2019 Inria
3  * SPDX-FileCopyrightText: 2019 Freie Universität Berlin
4  * SPDX-FileCopyrightText: 2019 Kaspar Schleiser <kaspar@schleiser.de>
5  * SPDX-License-Identifier: LGPL-2.1-only
6  */
7 
8 #pragma once
9 
20 /* This board provides an LSE */
21 #ifndef CONFIG_BOARD_HAS_LSE
22 #define CONFIG_BOARD_HAS_LSE 1
23 #endif
24 
25 /* This board provides an HSE */
26 #ifndef CONFIG_BOARD_HAS_HSE
27 #define CONFIG_BOARD_HAS_HSE 1
28 #endif
29 
30 /* The HSE provides a 12MHz clock */
31 #ifndef CONFIG_CLOCK_HSE
32 #define CONFIG_CLOCK_HSE MHZ(12)
33 #endif
34 
35 #include "periph_cpu.h"
36 #include "clk_conf.h"
37 #include "cfg_usb_otg_fs.h"
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
47 static const dma_conf_t dma_config[] = {
48  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
49  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
50 };
51 
52 #define DMA_0_ISR isr_dma2_stream3
53 #define DMA_1_ISR isr_dma2_stream2
54 
55 #define DMA_NUMOF ARRAY_SIZE(dma_config)
62 static const timer_conf_t timer_config[] = {
63  {
64  .dev = TIM5,
65  .max = 0xffffffff,
66  .rcc_mask = RCC_APB1ENR_TIM5EN,
67  .bus = APB1,
68  .irqn = TIM5_IRQn
69  }
70 };
71 
72 #define TIMER_0_ISR isr_tim5
73 
74 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
81 static const uart_conf_t uart_config[] = {
82  {
83  .dev = USART1,
84  .rcc_mask = RCC_APB2ENR_USART1EN,
85  .rx_pin = GPIO_PIN(PORT_B, 7),
86  .tx_pin = GPIO_PIN(PORT_B, 6),
87  .rx_af = GPIO_AF7,
88  .tx_af = GPIO_AF7,
89  .bus = APB2,
90  .irqn = USART1_IRQn,
91 #ifdef MODULE_PERIPH_DMA
92  .dma = DMA_STREAM_UNDEF,
93  .dma_chan = UINT8_MAX,
94 #endif
95  },
96 };
97 
98 #define UART_0_ISR (isr_usart1)
99 
100 #define UART_NUMOF ARRAY_SIZE(uart_config)
107 static const spi_conf_t spi_config[] = {
108  {
109  .dev = SPI1,
110  .mosi_pin = GPIO_PIN(PORT_A, 7),
111  .miso_pin = GPIO_PIN(PORT_A, 6),
112  .sclk_pin = GPIO_PIN(PORT_A, 5),
113  .cs_pin = GPIO_UNDEF,
114  .mosi_af = GPIO_AF5,
115  .miso_af = GPIO_AF5,
116  .sclk_af = GPIO_AF5,
117  .cs_af = GPIO_AF5,
118  .rccmask = RCC_APB2ENR_SPI1EN,
119  .apbbus = APB2,
120 #ifdef MODULE_PERIPH_DMA
121  .tx_dma = 0,
122  .tx_dma_chan = 3,
123  .rx_dma = 1,
124  .rx_dma_chan = 3,
125 #endif
126  }
127 };
128 
129 #define SPI_NUMOF ARRAY_SIZE(spi_config)
136 static const i2c_conf_t i2c_config[] = {
137  {
138  .dev = I2C2,
139  .speed = I2C_SPEED_NORMAL,
140  .scl_pin = GPIO_PIN(PORT_B, 10),
141  .sda_pin = GPIO_PIN(PORT_B, 11),
142  .scl_af = GPIO_AF4,
143  .sda_af = GPIO_AF4,
144  .bus = APB1,
145  .rcc_mask = RCC_APB1ENR_I2C2EN,
146  .clk = CLOCK_APB1,
147  .irqn = I2C2_ER_IRQn,
148  },
149 };
150 
151 #define I2C_0_ISR isr_i2c2_er
152 
153 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
156 #ifdef __cplusplus
157 }
158 #endif
159 
@ PORT_B
port B
Definition: periph_cpu.h:44
@ PORT_A
port A
Definition: periph_cpu.h:43
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:42
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:65
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:36
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:105
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:274
#define CLOCK_APB1
Half AHB clock.
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
I2C configuration structure.
Definition: periph_cpu.h:295
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:296
SPI device configuration.
Definition: periph_cpu.h:333
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:334
Timer device configuration.
Definition: periph_cpu.h:260
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:261
UART device configuration.
Definition: periph_cpu.h:214
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:215