periph_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2015-2020 Freie Universität Berlin
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
19 #include "cpu.h"
20 #include "periph_cpu.h"
21 #include "em_cmu.h"
22 #include "usbdev_cfg_otg_fs.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #ifndef CLOCK_HF
33 #define CLOCK_HF cmuSelect_HFXO
34 #endif
35 #ifndef CLOCK_CORE_DIV
36 #define CLOCK_CORE_DIV cmuClkDiv_1
37 #endif
38 #ifndef CLOCK_LFA
39 #define CLOCK_LFA cmuSelect_LFXO
40 #endif
41 #ifndef CLOCK_LFB
42 #define CLOCK_LFB cmuSelect_LFXO
43 #endif
44 #ifndef CLOCK_LFE
45 #define CLOCK_LFE cmuSelect_LFXO
46 #endif
53 static const adc_conf_t adc_config[] = {
54  {
55  .dev = ADC0,
56  .cmu = cmuClock_ADC0,
57  }
58 };
59 
60 static const adc_chan_conf_t adc_channel_config[] = {
61  {
62  .dev = 0,
63  .input = adcPosSelTEMP,
64  .reference = adcRef1V25,
65  .acq_time = adcAcqTime8
66  },
67  {
68  .dev = 0,
69  .input = adcPosSelAVDD,
70  .reference = adcRef5V,
71  .acq_time = adcAcqTime8
72  }
73 };
74 
75 #define ADC_DEV_NUMOF ARRAY_SIZE(adc_config)
76 #define ADC_NUMOF ARRAY_SIZE(adc_channel_config)
83 static const dac_conf_t dac_config[] = {
84  {
85  .dev = VDAC0,
86  .ref = vdacRefAvdd,
87  .cmu = cmuClock_VDAC0,
88  },
89 };
90 
91 static const dac_chan_conf_t dac_channel_config[] = {
92  {
93  .dev = 0,
94  .index = 0,
95  },
96 };
97 
98 #define DAC_DEV_NUMOF ARRAY_SIZE(dac_config)
99 #define DAC_NUMOF ARRAY_SIZE(dac_channel_config)
106 static const i2c_conf_t i2c_config[] = {
107  {
108  .dev = I2C0,
109  .sda_pin = GPIO_PIN(PC, 0),
110  .scl_pin = GPIO_PIN(PC, 1),
111  .loc = I2C_ROUTELOC0_SDALOC_LOC4 |
112  I2C_ROUTELOC0_SCLLOC_LOC4,
113  .cmu = cmuClock_I2C0,
114  .irq = I2C0_IRQn,
115  .speed = I2C_SPEED_NORMAL
116  },
117  {
118  .dev = I2C1,
119  .sda_pin = GPIO_PIN(PC, 7),
120  .scl_pin = GPIO_PIN(PC, 5),
121  .loc = I2C_ROUTELOC0_SDALOC_LOC0 |
122  I2C_ROUTELOC0_SCLLOC_LOC0,
123  .cmu = cmuClock_I2C1,
124  .irq = I2C1_IRQn,
125  .speed = I2C_SPEED_NORMAL
126  },
127  {
128  .dev = I2C2,
129  .sda_pin = GPIO_PIN(PI, 4),
130  .scl_pin = GPIO_PIN(PI, 5),
131  .loc = I2C_ROUTELOC0_SDALOC_LOC7 |
132  I2C_ROUTELOC0_SCLLOC_LOC7,
133  .cmu = cmuClock_I2C2,
134  .irq = I2C2_IRQn,
135  .speed = I2C_SPEED_NORMAL
136  }
137 };
138 
139 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
140 #define I2C_0_ISR isr_i2c0
141 #define I2C_1_ISR isr_i2c1
142 #define I2C_2_ISR isr_i2c2
149 #ifndef RTT_FREQUENCY
150 #define RTT_FREQUENCY (1U)
151 #endif
158 static const spi_dev_t spi_config[] = {
159  {
160  .dev = USART0,
161  .mosi_pin = GPIO_PIN(PE, 10),
162  .miso_pin = GPIO_PIN(PE, 11),
163  .clk_pin = GPIO_PIN(PE, 12),
164  .loc = USART_ROUTELOC0_TXLOC_LOC0 |
165  USART_ROUTELOC0_RXLOC_LOC0 |
166  USART_ROUTELOC0_CLKLOC_LOC0,
167  .cmu = cmuClock_USART0,
168  .irq = USART0_RX_IRQn
169  }
170 };
171 
172 #define SPI_NUMOF ARRAY_SIZE(spi_config)
181 static const timer_conf_t timer_config[] = {
182  {
183  .prescaler = {
184  .dev = WTIMER0,
185  .cmu = cmuClock_WTIMER0
186  },
187  .timer = {
188  .dev = WTIMER1,
189  .cmu = cmuClock_WTIMER1
190  },
191  .irq = WTIMER1_IRQn,
192  .channel_numof = 3
193  },
194  {
195  .prescaler = {
196  .dev = TIMER0,
197  .cmu = cmuClock_TIMER0
198  },
199  .timer = {
200  .dev = TIMER1,
201  .cmu = cmuClock_TIMER1
202  },
203  .irq = TIMER1_IRQn,
204  .channel_numof = 3
205  },
206  {
207  .prescaler = {
208  .dev = NULL,
209  .cmu = cmuClock_LETIMER0
210  },
211  .timer = {
212  .dev = LETIMER0,
213  .cmu = cmuClock_LETIMER0
214  },
215  .irq = LETIMER0_IRQn,
216  .channel_numof = 2
217  }
218 };
219 
220 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
221 #define TIMER_0_ISR isr_wtimer1
222 #define TIMER_1_ISR isr_timer1
223 #define TIMER_2_ISR isr_letimer0
230 static const uart_conf_t uart_config[] = {
231  {
232  .dev = USART4,
233  .rx_pin = GPIO_PIN(PH, 5),
234  .tx_pin = GPIO_PIN(PH, 4),
235  .loc = USART_ROUTELOC0_RXLOC_LOC4 |
236  USART_ROUTELOC0_TXLOC_LOC4,
237  .cmu = cmuClock_USART4,
238  .irq = USART4_RX_IRQn,
239  },
240  {
241  .dev = USART5,
242  .rx_pin = GPIO_PIN(PE, 9),
243  .tx_pin = GPIO_PIN(PE, 8),
244  .loc = USART_ROUTELOC0_RXLOC_LOC4 |
245  USART_ROUTELOC0_TXLOC_LOC4,
246  .cmu = cmuClock_USART5,
247  .irq = USART5_RX_IRQn,
248  }
249 };
250 
251 #define UART_NUMOF ARRAY_SIZE(uart_config)
252 #define UART_0_ISR_RX isr_usart4_rx
253 #define UART_1_ISR_RX isr_usart5_rx
256 #ifdef __cplusplus
257 }
258 #endif
259 
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:42
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:35
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:93
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:65
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:36
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:247
static const dac_conf_t dac_config[]
DAC configuration.
Definition: periph_conf.h:249
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:274
@ PC
port C
ADC channel configuration.
Definition: periph_cpu.h:382
uint8_t dev
device index
Definition: periph_cpu.h:383
ADC device configuration.
Definition: periph_cpu.h:374
ADC_TypeDef * dev
ADC device used.
Definition: periph_cpu.h:375
DAC line configuration data.
Definition: periph_cpu.h:300
I2C configuration structure.
Definition: periph_cpu.h:295
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:296
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:334
SPI device configuration.
Definition: periph_cpu.h:513
Timer device configuration.
Definition: periph_cpu.h:260
timer_dev_t prescaler
the lower neighboring timer (not initialized for LETIMER)
Definition: periph_cpu.h:552
void * dev
TIMER_TypeDef or LETIMER_TypeDef device used.
Definition: periph_cpu.h:545
UART device configuration.
Definition: periph_cpu.h:214
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:215
Common configuration for EFM32 OTG FS peripheral.