cpu_conf.h
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1 /*
2  * SPDX-FileCopyrightText: 2015-2017 Freie Universität Berlin
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
19 #include "cpu_conf_common.h"
20 
21 #include "em_device.h"
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
31 #define CPU_DEFAULT_IRQ_PRIO (1U)
32 #define CPU_IRQ_NUMOF (EXT_IRQ_COUNT + 1)
33 #define CPU_FLASH_BASE (FLASH_BASE)
40 #define FLASHPAGE_SIZE (FLASH_PAGE_SIZE)
41 #define FLASHPAGE_NUMOF (FLASH_SIZE / FLASH_PAGE_SIZE)
42 /* The minimum block size which can be written is 4B. However, the erase
43  * block is always FLASHPAGE_SIZE.
44  */
45 #define FLASHPAGE_WRITE_BLOCK_SIZE (4U)
46 /* Writing should be always 4 bytes aligned */
47 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
54 #ifdef BITBAND_RAM_BASE
55 #define CPU_HAS_BITBAND 1
56 #endif
59 #ifdef __cplusplus
60 }
61 #endif
62