board.h
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1 /*
2  * SPDX-FileCopyrightText: 2014 Eistec AB
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
18 #include "cpu.h"
19 #include "periph_conf.h"
20 #include "mulle-nvram.h"
21 
22 /* Use the on board RTC 32kHz clock for LPTMR clocking. */
23 #undef LPTIMER_CLKSRC
25 #define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K
26 
28 #define DISABLE_WDOG 1
29 
33 #define STDIO_UART_DEV UART_DEV(1)
34 
39 #if 0
40 /* LPTMR xtimer configuration */
41 /* WIP, Use PIT for now */
42 #define XTIMER_DEV (TIMER_LPTMR_DEV(0))
43 /* LPTMR is 16 bits wide */
44 #define XTIMER_WIDTH (16)
45 #define XTIMER_BACKOFF (4)
46 #define XTIMER_ISR_BACKOFF (4)
47 #define XTIMER_HZ (32768ul)
48 #else
49 /* PIT xtimer configuration */
50 #define XTIMER_DEV (TIMER_PIT_DEV(0))
51 #define XTIMER_CHAN (0)
52 #define XTIMER_BACKOFF (40)
53 #define XTIMER_ISR_BACKOFF (40)
54 #endif
61 #define LED_PORT PTC
62 #define LED0_BIT (15)
63 #define LED1_BIT (14)
64 #define LED2_BIT (13)
65 
66 #define LED0_PIN GPIO_PIN(PORT_C, LED0_BIT)
67 #define LED1_PIN GPIO_PIN(PORT_C, LED1_BIT)
68 #define LED2_PIN GPIO_PIN(PORT_C, LED2_BIT)
69 
70 #define LED0_ON (LED_PORT->PSOR = (1 << LED0_BIT))
71 #define LED0_OFF (LED_PORT->PCOR = (1 << LED0_BIT))
72 #define LED0_TOGGLE (LED_PORT->PTOR = (1 << LED0_BIT))
73 
74 #define LED1_ON (LED_PORT->PSOR = (1 << LED1_BIT))
75 #define LED1_OFF (LED_PORT->PCOR = (1 << LED1_BIT))
76 #define LED1_TOGGLE (LED_PORT->PTOR = (1 << LED1_BIT))
77 
78 #define LED2_ON (LED_PORT->PSOR = (1 << LED2_BIT))
79 #define LED2_OFF (LED_PORT->PCOR = (1 << LED2_BIT))
80 #define LED2_TOGGLE (LED_PORT->PTOR = (1 << LED2_BIT))
83 #ifdef __cplusplus
84 extern "C" {
85 #endif
86 
87 #ifdef __cplusplus
88 }
89 #endif
90 
100 #define AT86RF2XX_PARAM_CS SPI_HWCS(1)
101 #define AT86RF2XX_PARAM_INT GPIO_PIN(PORT_B, 9)
102 #define AT86RF2XX_PARAM_SLEEP GPIO_PIN(PORT_E, 6)
103 #define AT86RF2XX_PARAM_RESET GPIO_PIN(PORT_C, 12)
110 #define LIS3DH_PARAM_INT1 GPIO_PIN(PORT_C, 18)
111 #define LIS3DH_PARAM_INT2 GPIO_PIN(PORT_C, 17)
112 #define LIS3DH_PARAM_CS SPI_HWCS(0)
113 #define LIS3DH_PARAM_CLK (SPI_CLK_5MHZ)
120 #define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17)
121 #define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7)
122 #define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16)
129 #define MULLE_NVRAM_SPI_DEV SPI_DEV(0)
130 #define MULLE_NVRAM_SPI_CLK SPI_CLK_5MHZ
131 #define MULLE_NVRAM_SPI_CS SPI_HWCS(3)
132 #define MULLE_NVRAM_CAPACITY 512
133 #define MULLE_NVRAM_SPI_ADDRESS_COUNT 1
140 #define MULLE_NOR_SPI_DEV SPI_DEV(0)
141 #define MULLE_NOR_SPI_CLK SPI_CLK_5MHZ
142 #define MULLE_NOR_SPI_CS SPI_HWCS(2)
148 #define MTD_0 mtd_dev_get(0)
155 #define MULLE_VBAT_ADC_LINE ADC_LINE(6)
156 #define MULLE_VCHR_ADC_LINE ADC_LINE(7)
Peripheral MCU configuration for the Zigduino board.
NVRAM offsets for the Eistec Mulle IoT board.