board.h

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/*
 * SPDX-FileCopyrightText: 2017 Thomas Stilwell <stilwellt@openlabs.co>
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once
 
#include "cpu.h"
#include "periph_conf.h"
 
#ifdef __cplusplus
extern "C"
{
#endif
 
/*
 * NMI shares a pin with DAC output and ADC input. Holding the pin low during
 * reset will cause a hang unless NMI is disabled. It can be enabled in
 * applications where the pin is not held low during reset.
 */
#define KINETIS_FOPT 0xFB /* disable NMI (0xFF to enable) */
 
#define LED0_PIN           GPIO_PIN(PORT_B,  0)
#define LED0_MASK          (1 << 0)
#define LED0_ON            (GPIOB->PCOR = LED0_MASK)
#define LED0_OFF           (GPIOB->PSOR = LED0_MASK)
#define LED0_TOGGLE        (GPIOB->PTOR = LED0_MASK)
#if IS_ACTIVE(KINETIS_XTIMER_SOURCE_PIT)
/* PIT xtimer configuration */
#define XTIMER_DEV                  (TIMER_PIT_DEV(0))
#define XTIMER_CHAN                 (0)
/* Default xtimer settings should work on the PIT */
#else
/* LPTMR xtimer configuration */
#define XTIMER_DEV                  (TIMER_LPTMR_DEV(0))
#define XTIMER_CHAN                 (0)
/* LPTMR is 16 bits wide and runs at 32768 Hz (clocked by the RTC) */
#define XTIMER_WIDTH                (16)
#define XTIMER_BACKOFF              (16)
#define XTIMER_ISR_BACKOFF          (5)
#define XTIMER_HZ                   (32768ul)
#endif
#ifndef PTB3_OUTPUT_OSC32K
#define PTB3_OUTPUT_OSC32K          (0)
#endif
 
#ifndef PTB3_OUTPUT_OSCERCLK
#define PTB3_OUTPUT_OSCERCLK        (0)
#endif
 
#ifdef __cplusplus
}
#endif