Default STM32U5 clock configuration. More...
Default STM32U5 clock configuration.
Definition in file cfg_clock_default.h.
 Include dependency graph for cfg_clock_default.h:Go to the source code of this file.
U5 clock system configuration | |
| #define | CONFIG_CLOCK_PLL_SRC_MSI 1 /* Use MSI as input clock by default */ | 
| #define | CONFIG_CLOCK_PLL_SRC_HSE 0 | 
| #define | CONFIG_CLOCK_PLL_SRC_HSI 0 | 
| #define | CLOCK_PLL_SRC (CONFIG_CLOCK_HSI) | 
| #define | CONFIG_CLOCK_PLL_M (2) /* HSI/HSE at 16MHz */ | 
| #define | CONFIG_CLOCK_PLL_N (40) | 
| #define | CONFIG_CLOCK_PLL_Q (2) | 
| #define | CONFIG_CLOCK_PLL_R (2) | 
| #define | CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 160MHz */ | 
| #define | CONFIG_CLOCK_APB1_DIV (4) | 
| #define | CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 160MHz */ | 
| #define | CONFIG_CLOCK_APB2_DIV (2) | 
| #define | CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 160MHz */ |