atomic_utils_arch.h
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1 /*
2  * SPDX-FileCopyrightText: 2020 Otto-von-Guericke-Universität Magdeburg
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
19 #include "periph_cpu.h"
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
25 #ifndef DOXYGEN
26 
27 /* clang provides no built-in atomic access to regular variables */
28 #ifndef __clang__
29 
30 #define HAS_ATOMIC_LOAD_U8
31 static inline uint8_t atomic_load_u8(const volatile uint8_t *var)
32 {
33  return __atomic_load_1(var, __ATOMIC_SEQ_CST);
34 }
35 
36 #define HAS_ATOMIC_LOAD_U16
37 static inline uint16_t atomic_load_u16(const volatile uint16_t *var)
38 {
39  return __atomic_load_2(var, __ATOMIC_SEQ_CST);
40 }
41 
42 #define HAS_ATOMIC_LOAD_U32
43 static inline uint32_t atomic_load_u32(const volatile uint32_t *var)
44 {
45  return __atomic_load_4(var, __ATOMIC_SEQ_CST);
46 }
47 
48 #define HAS_ATOMIC_STORE_U8
49 static inline void atomic_store_u8(volatile uint8_t *dest, uint8_t val)
50 {
51  __atomic_store_1(dest, val, __ATOMIC_SEQ_CST);
52 }
53 
54 #define HAS_ATOMIC_STORE_U16
55 static inline void atomic_store_u16(volatile uint16_t *dest, uint16_t val)
56 {
57  __atomic_store_2(dest, val, __ATOMIC_SEQ_CST);
58 }
59 
60 #define HAS_ATOMIC_STORE_U32
61 static inline void atomic_store_u32(volatile uint32_t *dest, uint32_t val)
62 {
63  __atomic_store_4(dest, val, __ATOMIC_SEQ_CST);
64 }
65 
66 #endif /* __clang__ */
67 #endif /* DOXYGEN */
68 
69 #ifdef __cplusplus
70 }
71 #endif
72 
static void atomic_store_u8(volatile uint8_t *dest, uint8_t val)
Store an uint8_t atomically.
static uint32_t atomic_load_u32(const volatile uint32_t *var)
Load an uint32_t atomically.
static uint16_t atomic_load_u16(const volatile uint16_t *var)
Load an uint16_t atomically.
static uint8_t atomic_load_u8(const volatile uint8_t *var)
Load an uint8_t atomically.
static void atomic_store_u16(volatile uint16_t *dest, uint16_t val)
Store an uint16_t atomically.
static void atomic_store_u32(volatile uint32_t *dest, uint32_t val)
Store an uint32_t atomically.
Shared CPU specific definitions for the STM32 family.