cpu_conf.h

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/*
 * SPDX-FileCopyrightText: 2020 iosabi
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once
 
#include "cpu_conf_common.h"
 
#include "vendor/QN908XC.h"
#include "vendor/QN908XC_features.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define CPU_DEFAULT_IRQ_PRIO    (1U)
#define CPU_IRQ_NUMOF           (NUMBER_OF_INT_VECTORS - 16)
#define CPU_FLASH_BASE          (QN908X_ROM_START_ADDR)
#define CPU_HAS_BITBAND 1
#if !defined(CONFIG_BOARD_HAS_XTAL32K) || DOXYGEN
#define CONFIG_BOARD_HAS_XTAL32K        0
#endif
 
#ifdef DOXYGEN
#define CONFIG_CPU_CLK_32K_XTAL
#define CONFIG_CPU_CLK_32K_RCO
#endif  /* def DOXYGEN */
/* Default 32K clock selector config. */
#if !defined(CONFIG_CPU_CLK_32K_XTAL) && !defined(CONFIG_CPU_CLK_32K_RCO)
#if CONFIG_BOARD_HAS_XTAL32K
#define CONFIG_CPU_CLK_32K_XTAL         1
#else
#define CONFIG_CPU_CLK_32K_RCO          1
#endif
#endif
 
#ifndef CONFIG_BOARD_HAS_XTAL
#define CONFIG_BOARD_HAS_XTAL           0
#endif
 
#ifdef DOXYGEN
#define CONFIG_CPU_CLK_XTAL_16M
#define CONFIG_CPU_CLK_XTAL_32M
#endif  /* def DOXYGEN */
/* Default XTAL setting. */
#if CONFIG_BOARD_HAS_XTAL && \
    !defined(CONFIG_BOARD_HAS_XTAL_16M) && !defined(CONFIG_BOARD_HAS_XTAL_32M)
#define CONFIG_BOARD_HAS_XTAL_32M        1
#endif
 
#ifndef CONFIG_CPU_CLK_OSC32M_DIV
#define CONFIG_CPU_CLK_OSC32M_DIV    0
#endif
 
#ifndef CONFIG_CPU_CLK_XTAL_DIV
#define CONFIG_CPU_CLK_XTAL_DIV      0
#endif
 
#ifdef DOXYGEN
#define CONFIG_CPU_CLK_SYS_XTAL
#define CONFIG_CPU_CLK_SYS_OSC32M
#define CONFIG_CPU_CLK_SYS_32K
#endif  /* def DOXYGEN */
/* Default system clock configuration selector */
#if !defined(CONFIG_CPU_CLK_SYS_XTAL) && !defined(CONFIG_CPU_CLK_SYS_OSC32M) && \
    !defined(CONFIG_CPU_CLK_SYS_32K)
#if CONFIG_BOARD_HAS_XTAL
#define CONFIG_CPU_CLK_SYS_XTAL      1
#else
#define CONFIG_CPU_CLK_SYS_OSC32M       1
#endif
#endif
 
#ifndef CONFIG_CPU_CLK_AHB_DIV
#define CONFIG_CPU_CLK_AHB_DIV       1u
#endif
 
#ifndef CONFIG_CPU_CLK_APB_DIV
#define CONFIG_CPU_CLK_APB_DIV       1u
#endif
 
#define QN908X_CRP_PROTECT_PAGES(X) (255 - (X))
 
#define QN908X_CRP_MASS_ERASE_ALLOW     (0x800)
#define QN908X_CRP_MASS_ERASE_DISALLOW  (0x400)
 
#define QN908X_CRP_PAGE_ERASE_WRITE_ALLOW     (0x2000)
#define QN908X_CRP_PAGE_ERASE_WRITE_DISALLOW  (0x1000)
 
#define QN908X_CRP_FLASH_READ_ALLOW     (0x8000)
#define QN908X_CRP_FLASH_READ_DISALLOW  (0x4000)
 
#define QN908X_CRP_ISP_ENTRY_ALLOW     (0x20000)
#define QN908X_CRP_ISP_ENTRY_DISALLOW  (0x10000)
 
#define QN908X_CRP_EXTERNAL_ACCESS_ALLOW     (0x80000)
#define QN908X_CRP_EXTERNAL_ACCESS_DISALLOW  (0x40000)
 
#ifndef QN908X_CRP
#define QN908X_CRP \
    (QN908X_CRP_PROTECT_PAGES(0) \
     | QN908X_CRP_MASS_ERASE_ALLOW \
     | QN908X_CRP_PAGE_ERASE_WRITE_ALLOW \
     | QN908X_CRP_FLASH_READ_ALLOW \
     | QN908X_CRP_ISP_ENTRY_ALLOW \
     | QN908X_CRP_EXTERNAL_ACCESS_ALLOW)
#endif  /* QN908X_CRP */
 
#define CORTEXM_VECTOR_RESERVED_0X20 QN908X_CRP
 
/* Safety checks that the QN908X_CRP value is valid. */
#if !(QN908X_CRP & QN908X_CRP_MASS_ERASE_ALLOW) == \
    !(QN908X_CRP & QN908X_CRP_MASS_ERASE_DISALLOW)
#error "Must select exactly one of QN908X_CRP_MASS_ERASE_* in the QN908X_CRP"
#endif
#if !(QN908X_CRP & QN908X_CRP_PAGE_ERASE_WRITE_ALLOW) == \
    !(QN908X_CRP & QN908X_CRP_PAGE_ERASE_WRITE_DISALLOW)
#error \
    "Must select exactly one of QN908X_CRP_PAGE_ERASE_WRITE_* in the QN908X_CRP"
#endif
#if !(QN908X_CRP & QN908X_CRP_FLASH_READ_ALLOW) == \
    !(QN908X_CRP & QN908X_CRP_FLASH_READ_DISALLOW)
#error "Must select exactly one of QN908X_CRP_FLASH_READ_* in the QN908X_CRP"
#endif
#if !(QN908X_CRP & QN908X_CRP_ISP_ENTRY_ALLOW) == \
    !(QN908X_CRP & QN908X_CRP_ISP_ENTRY_DISALLOW)
#error "Must select exactly one of QN908X_CRP_ISP_ENTRY_* in the QN908X_CRP"
#endif
#if !(QN908X_CRP & QN908X_CRP_EXTERNAL_ACCESS_ALLOW) == \
    !(QN908X_CRP & QN908X_CRP_EXTERNAL_ACCESS_DISALLOW)
#error \
    "Must select exactly one of QN908X_CRP_EXTERNAL_ACCESS_* in the QN908X_CRP"
#endif
 
#ifdef __cplusplus
}
#endif