compat_layer.h
Go to the documentation of this file.
1 /*
2  * SPDX-FileCopyrightText: 2025 Tom Hert <git@annsann.eu>
3  * SPDX-FileCopyrightText: 2025 HAW Hamburg
4  * SPDX-License-Identifier: LGPL-2.1-only
5  */
6 
7 #pragma once
8 
19 #include "periph_cpu.h"
20 
21 #ifdef RP2350_USE_RISCV
22 # include "xh3irq.h"
23 #endif
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 static inline void rp_irq_enable(uint32_t irq_no)
34 {
35 #ifdef RP2350_USE_RISCV
36  xh3irq_enable_irq(irq_no);
37 #else
38  NVIC_EnableIRQ(irq_no);
39 #endif
40 }
41 
45 static inline void rp_end_isr(void)
46 {
47 #ifdef RP2350_USE_ARM
48  cortexm_isr_end();
49 #endif
50 }
51 
52 #ifdef __cplusplus
53 }
54 #endif
55 
rp_end_isr
static void rp_end_isr(void)
Called upon the end of an ISR.
Definition: compat_layer.h:45
rp_irq_enable
static void rp_irq_enable(uint32_t irq_no)
Enable the given IRQ.
Definition: compat_layer.h:33
cortexm_isr_end
static void cortexm_isr_end(void)
Trigger a conditional context scheduler run / context switch.
Definition: cpu.h:176
periph_cpu.h
Shared CPU specific definitions for the STM32 family.
xh3irq.h
xh3irq.h interrupt controller support
xh3irq_enable_irq
void xh3irq_enable_irq(uint32_t irq_no)
Enable the given IRQ number.