periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2017 Freie Universität Berlin
3  * 2017 Inria
4  * 2017 HAW-Hamburg
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
11 #pragma once
12 
25 /* Add specific clock configuration (HSE, LSE) for this board here */
26 #ifndef CONFIG_BOARD_HAS_LSE
27 #define CONFIG_BOARD_HAS_LSE 1
28 #endif
29 
30 #include "periph_cpu.h"
31 #include "clk_conf.h"
32 #include "cfg_i2c1_pb8_pb9.h"
33 #include "cfg_rtt_default.h"
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
43 static const dma_conf_t dma_config[] = {
44  { .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX | USART3_TX */
45  { .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */
46  { .stream = 3 }, /* DMA1 Channel 4 - USART1_TX */
47  { .stream = 6 }, /* DMA1 Channel 7 - USART2_TX */
48 };
49 
50 #define DMA_0_ISR isr_dma1_channel2
51 #define DMA_1_ISR isr_dma1_channel3
52 #define DMA_2_ISR isr_dma1_channel4
53 #define DMA_3_ISR isr_dma1_channel7
54 
55 #define DMA_NUMOF ARRAY_SIZE(dma_config)
62 static const timer_conf_t timer_config[] = {
63  {
64  .dev = TIM5,
65  .max = 0xffffffff,
66  .rcc_mask = RCC_APB1ENR1_TIM5EN,
67  .bus = APB1,
68  .irqn = TIM5_IRQn
69  }
70 };
71 
72 #define TIMER_0_ISR isr_tim5
73 
74 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
81 static const uart_conf_t uart_config[] = {
82  {
83  .dev = USART2,
84  .rcc_mask = RCC_APB1ENR1_USART2EN,
85  .rx_pin = GPIO_PIN(PORT_A, 3),
86  .tx_pin = GPIO_PIN(PORT_A, 2),
87  .rx_af = GPIO_AF7,
88  .tx_af = GPIO_AF7,
89  .bus = APB1,
90  .irqn = USART2_IRQn,
91  .type = STM32_USART,
92  .clk_src = 0, /* Use APB clock */
93 #ifdef MODULE_PERIPH_DMA
94  .dma = 3,
95  .dma_chan = 2
96 #endif
97  },
98  {
99  .dev = USART3,
100  .rcc_mask = RCC_APB1ENR1_USART3EN,
101  .rx_pin = GPIO_PIN(PORT_C, 11),
102  .tx_pin = GPIO_PIN(PORT_C, 10),
103  .rx_af = GPIO_AF7,
104  .tx_af = GPIO_AF7,
105  .bus = APB1,
106  .irqn = USART3_IRQn,
107  .type = STM32_USART,
108  .clk_src = 0, /* Use APB clock */
109 #ifdef MODULE_PERIPH_DMA
110  .dma = 0,
111  .dma_chan = 2
112 #endif
113  },
114  {
115  .dev = USART1,
116  .rcc_mask = RCC_APB2ENR_USART1EN,
117  .rx_pin = GPIO_PIN(PORT_A, 10),
118  .tx_pin = GPIO_PIN(PORT_A, 9),
119  .rx_af = GPIO_AF7,
120  .tx_af = GPIO_AF7,
121  .bus = APB2,
122  .irqn = USART1_IRQn,
123  .type = STM32_USART,
124  .clk_src = 0, /* Use APB clock */
125 #ifdef MODULE_PERIPH_DMA
126  .dma = 2,
127  .dma_chan = 2
128 #endif
129  }
130 };
131 
132 #define UART_0_ISR (isr_usart2)
133 #define UART_1_ISR (isr_usart3)
134 #define UART_2_ISR (isr_usart1)
135 
136 #define UART_NUMOF ARRAY_SIZE(uart_config)
143 static const pwm_conf_t pwm_config[] = {
144  {
145  .dev = TIM2,
146  .rcc_mask = RCC_APB1ENR1_TIM2EN,
147  .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
148  { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
149  { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
150  { .pin = GPIO_PIN(PORT_B, 11), .cc_chan = 3} },
151  .af = GPIO_AF1,
152  .bus = APB1
153  },
154  {
155  .dev = TIM3,
156  .rcc_mask = RCC_APB1ENR1_TIM3EN,
157  .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
158  { .pin = GPIO_UNDEF, .cc_chan = 0 },
159  { .pin = GPIO_UNDEF, .cc_chan = 0 },
160  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
161  .af = GPIO_AF2,
162  .bus = APB1
163  },
164  {
165  .dev = TIM8,
166  .rcc_mask = RCC_APB2ENR_TIM8EN,
167  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
168  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
169  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
170  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
171  .af = GPIO_AF3,
172  .bus = APB2
173  }
174 };
175 
176 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
183 static const spi_conf_t spi_config[] = {
184  {
185  .dev = SPI1,
186  .mosi_pin = GPIO_PIN(PORT_A, 7),
187  .miso_pin = GPIO_PIN(PORT_A, 6),
188  .sclk_pin = GPIO_PIN(PORT_A, 5),
189  .cs_pin = SPI_CS_UNDEF,
190  .mosi_af = GPIO_AF5,
191  .miso_af = GPIO_AF5,
192  .sclk_af = GPIO_AF5,
193  .cs_af = GPIO_AF5,
194  .rccmask = RCC_APB2ENR_SPI1EN,
195  .apbbus = APB2,
196 #ifdef MODULE_PERIPH_DMA
197  .tx_dma = 1,
198  .tx_dma_chan = 1,
199  .rx_dma = 0,
200  .rx_dma_chan = 1,
201 #endif
202  }
203 };
204 
205 #define SPI_NUMOF ARRAY_SIZE(spi_config)
236 static const adc_conf_t adc_config[] = {
237  {GPIO_PIN(PORT_A, 0), 0, 5}, /*< ADC12_IN5 */
238  {GPIO_PIN(PORT_A, 1), 0, 6}, /*< ADC12_IN6 */
239  {GPIO_PIN(PORT_A, 4), 1, 9}, /*< ADC12_IN9 */
240  {GPIO_PIN(PORT_B, 0), 1, 15}, /*< ADC12_IN15 */
241  {GPIO_PIN(PORT_C, 1), 2, 2}, /*< ADC123_IN2 */
242  {GPIO_PIN(PORT_C, 0), 2, 1}, /*< ADC123_IN1 */
243  {GPIO_UNDEF, 0, 18}, /* VBAT */
244 };
245 
246 #define VBAT_ADC ADC_LINE(6)
247 #define ADC_NUMOF ARRAY_SIZE(adc_config)
250 #ifdef __cplusplus
251 }
252 #endif
253 
@ PORT_B
port B
Definition: periph_cpu.h:47
@ PORT_C
port C
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:46
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:45
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:38
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:96
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:39
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:221
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:236
Common configuration for STM32 I2C.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:102
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:106
@ GPIO_AF3
use alternate function 3
Definition: cpu_gpio.h:104
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:108
@ STM32_USART
STM32 USART module type.
Definition: cpu_uart.h:37
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:362
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
ADC device configuration.
Definition: periph_cpu.h:377
DMA configuration.
Definition: cpu_dma.h:31
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:54
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:336
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:337
Timer device configuration.
Definition: periph_cpu.h:263
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:264
UART device configuration.
Definition: periph_cpu.h:217
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:218