cc26xx_cc13xx.h

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/*
 * Copyright (C) 2016 Leon George
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#pragma once
 
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef volatile uint8_t reg8_t;
typedef volatile uint16_t reg16_t;
typedef volatile uint32_t reg32_t;
 
typedef struct {
    reg8_t LOW; 
    reg8_t HIGH; 
} reg8_m4_t;
 
typedef reg16_t reg8_m8_t;
 
typedef struct {
    reg32_t LOW; 
    reg32_t HIGH; 
} reg32_m16_t;
 
typedef enum IRQn {
    /******  Cortex-M4 Processor Exceptions Numbers ****************************/
    ResetHandler_IRQn     = -15, 
    NonMaskableInt_IRQn   = -14, 
    HardFault_IRQn        = -13, 
    MemoryManagement_IRQn = -12, 
    BusFault_IRQn         = -11, 
    UsageFault_IRQn       = -10, 
    SVCall_IRQn           = - 5, 
    DebugMonitor_IRQn     = - 4, 
    PendSV_IRQn           = - 2, 
    SysTick_IRQn          = - 1, 
    /******  CC13x2 specific Interrupt Numbers *********************************/
    EDGE_DETECT_IRQN      =   0, 
    I2C_IRQN              =   1, 
    RF_CPE1_IRQN          =   2, 
    PKA_IRQN              =   3, 
    AON_RTC_IRQN          =   4, 
    UART0_IRQN            =   5, 
    AON_AUX_SWEV0_IRQN    =   6, 
    SSI0_IRQN             =   7, 
    SSI1_IRQN             =   8, 
    RF_CPE0_IRQN          =   9, 
    RF_HW_IRQN            =  10, 
    RF_CMD_ACK_IRQN       =  11, 
    I2S_IRQN              =  12, 
    AON_AUX_SWEV1_IRQN    =  13, 
    WATCHDOG_IRQN         =  14, 
    GPTIMER_0A_IRQN       =  15, 
    GPTIMER_0B_IRQN       =  16, 
    GPTIMER_1A_IRQN       =  17, 
    GPTIMER_1B_IRQN       =  18, 
    GPTIMER_2A_IRQN       =  19, 
    GPTIMER_2B_IRQN       =  20, 
    GPTIMER_3A_IRQN       =  21, 
    GPTIMER_3B_IRQN       =  22, 
    CRYPTO_IRQN           =  23, 
    UDMA_IRQN             =  24, 
    UDMA_ERR_IRQN         =  25, 
    FLASH_CTRL_IRQN       =  26, 
    SW0_IRQN              =  27, 
    AUX_COMBO_IRQN        =  28, 
    AON_PRG0_IRQN         =  29, 
    PROG_IRQN             =  30, 
    AUX_COMPA_IRQN        =  31, 
    AUX_ADC_IRQN          =  32, 
    TRNG_IRQN             =  33, 
#ifdef CPU_VARIANT_X2
    OSC_IRQN              =  34, 
    AUX_TIMER2_IRQN       =  35, 
    UART1_IRQN            =  36, 
    BATMON_IRQN           =  37, 
    IRQN_COUNT            = (BATMON_IRQN + 1) 
#else
    IRQN_COUNT            = (TRNG_IRQN + 1) 
#endif
 
} IRQn_Type;
 
#define __MPU_PRESENT          1      
#define __NVIC_PRIO_BITS       3      
#define __Vendor_SysTickConfig 0      
#define RCOSC48M_FREQ               48000000 
#define RCOSC24M_FREQ               24000000 
#ifdef CPU_VARIANT_X2
#include <core_cm4.h>
#else
#include <core_cm3.h>
#endif
#define FLASH_BASE         0x00000000 
#define PERIPH_BASE        0x40000000 
#define PERIPH_BASE_NONBUF 0x60000000 
#define ROM_HARD_API_BASE  0x10000048 
#define ROM_API_TABLE      ((uint32_t *) 0x10000180) 
#define ADI_DIR            0x00000000
#define ADI_SET            0x00000010
#define ADI_CLR            0x00000020
#define ADI_MASK4B         0x00000040
#define ADI_MASK8B         0x00000060
#define ADI_MASK16B        0x00000080
#ifdef __cplusplus
}
#endif