cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universität Berlin
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
10 #pragma once
11 
23 #include <stdint.h>
24 
25 #include "cpu_conf.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
31 #ifdef Doxygen
36 #define STM32_BOOTLOADER_ADDR
37 #endif
38 
44 #define CPUID_LEN (12U)
45 
49 #ifndef CPUID_ADDR
50 #define CPUID_ADDR (UID_BASE)
51 #endif
52 
56 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
57  defined(CPU_FAM_STM32F3)
58 #define CLOCK_LSI (40000U)
59 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
60 #define CLOCK_LSI (37000U)
61 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
62  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
63  defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
64  defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
65  defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
66  defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
67 #define CLOCK_LSI (32000U)
68 #else
69 #error "error: LSI clock speed not defined for your target CPU"
70 #endif
71 
72 /* if CPU has APB1 bus */
73 #if defined(CPU_FAM_STM32G4) || \
74  defined(CPU_FAM_STM32L4) || \
75  defined(CPU_FAM_STM32L5) || \
76  defined(CPU_FAM_STM32U5) || \
77  defined(CPU_FAM_STM32WB) || \
78  defined(CPU_FAM_STM32WL)
79  #define APB1_PERIPH_EN RCC->APB1ENR1
80  #define APB12_PERIPH_EN RCC->APB1ENR2
81 #elif defined(CPU_FAM_STM32C0) || \
82  defined(CPU_FAM_STM32G0)
83  #define APB1_PERIPH_EN RCC->APBENR1
84  #define APB12_PERIPH_EN RCC->APBENR2
85 #elif defined(CPU_FAM_STM32MP1)
86  #define APB1_PERIPH_EN RCC->MC_APB1ENSETR
87  #define APB1_PERIPH_DIS RCC->MC_APB1ENCLRR
88 #elif defined(APB1PERIPH_BASE) || \
89  defined(CPU_FAM_STM32F0) || \
90  defined(CPU_FAM_STM32L0)
91  #define APB1_PERIPH_EN RCC->APB1ENR
92 #endif
93 
94 /* if CPU has APB2 bus */
95 #if defined(CPU_FAM_STM32MP1)
96  #define APB2_PERIPH_EN RCC->MC_APB2ENSETR
97  #define APB2_PERIPH_DIS RCC->MC_APB2ENCLRR
98 #elif defined(APB2PERIPH_BASE) || \
99  defined(CPU_FAM_STM32F0) || \
100  defined(CPU_FAM_STM32L0)
101  #define APB2_PERIPH_EN RCC->APB2ENR
102 #endif
103 
104 /* if CPU has APB3 bus */
105 #if defined(CPU_FAM_STM32WB)
106  /* CPU has APB3, but no periph enable registers for the bus. */
107  #undef APB3_PERIPH_EN /* not defined */
108 #elif defined(APB3PERIPH_BASE) || \
109  defined(APB3PERIPH_BASE_S)
110  #define APB3_PERIPH_EN RCC->APB3ENR
111 #endif
112 
113 /* if CPU has AHB/AHB1 bus */
114 #if defined(AHBPERIPH_BASE) || \
115  defined(CPU_FAM_STM32F3)
116  #define AHB_PERIPH_EN RCC->AHBENR
117 #elif defined(CPU_FAM_STM32MP1)
118  /* CPU has AHB1, but no periph enable registers for the bus. */
119  #undef AHB1_PERIPH_EN /* not defined */
120  #undef AHB1_PERIPH_DIS /* not defined */
121 #elif defined(AHB1PERIPH_BASE)
122  #define AHB1_PERIPH_EN RCC->AHB1ENR
123 #endif
124 
125 /* if CPU has AHB2 bus */
126 #if defined(CPU_FAM_STM32F0) || \
127  defined(CPU_FAM_STM32F3)
128  /* CPU has AHB2, but no periph enable registers for the bus. */
129  #undef AHB2_PERIPH_EN /* not defined */
130 #elif defined(CPU_FAM_STM32U5)
131  #define AHB2_PERIPH_EN RCC->AHB2ENR1
132  #define AHB22_PERIPH_EN RCC->AHB2ENR2
133 #elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB2_SUPPORT)
134  #define AHB2_PERIPH_EN RCC->AHB2ENR
135 #elif defined(CPU_FAM_STM32MP1)
136  #define AHB2_PERIPH_EN RCC->MC_AHB2ENSETR
137  #define AHB2_PERIPH_DIS RCC->MC_AHB2ENCLRR
138 #elif defined(AHB2PERIPH_BASE)
139  #define AHB2_PERIPH_EN RCC->AHB2ENR
140 #endif
141 
142 /* if CPU has AHB3 bus */
143 #if defined(CPU_FAM_STM32F3)
144  /* CPU has AHB3, but no periph enable registers for the bus. */
145  #undef AHB3_PERIPH_EN /* not defined */
146 #elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB3_SUPPORT)
147  #define AHB3_PERIPH_EN RCC->AHB3ENR
148 #elif defined(CPU_FAM_STM32MP1)
149  #define AHB3_PERIPH_EN RCC->MC_AHB3ENSETR
150  #define AHB3_PERIPH_DIS RCC->MC_AHB3ENCLRR
151 #elif defined(AHB3PERIPH_BASE) || \
152  defined(AHB3PERIPH_BASE_S) || \
153  defined(CPU_FAM_STM32F2) || \
154  defined(CPU_FAM_STM32F7) || \
155  defined(CPU_FAM_STM32G4) || \
156  defined(CPU_FAM_STM32L4)
157  #define AHB3_PERIPH_EN RCC->AHB3ENR
158 #endif
159 
160 /* if CPU has AHB4 bus */
161 #if defined(CPU_FAM_STM32MP1)
162  #define AHB4_PERIPH_EN RCC->MC_AHB4ENSETR
163  #define AHB4_PERIPH_DIS RCC->MC_AHB4ENCLRR
164 #elif defined(AHB4PERIPH_BASE)
165  /* AHB3ENR is not a typo here. It controls both AHB3 and AHB4. */
166  #define AHB4_PERIPH_EN RCC->AHB3ENR
167 #endif
168 
169 /* if CPU has IOP bus */
170 #if defined(IOPPERIPH_BASE) || \
171  defined(RCC_IOPENR_GPIOAEN) || \
172  defined(RCC_IOPENR_IOPAEN)
173  #define IOP_PERIPH_EN RCC->IOPENR
174 #endif
175 
179 typedef enum {
180 #if defined(APB1_PERIPH_EN)
181  APB1,
182 #endif
183 #if defined(APB12_PERIPH_EN)
184  APB12,
185 #endif
186 #if defined(APB2_PERIPH_EN)
187  APB2,
188 #endif
189 #if defined(APB3_PERIPH_EN)
190  APB3,
191 #endif
192 #if defined(AHB_PERIPH_EN)
193  AHB,
194 #endif
195 #if defined(AHB1_PERIPH_EN)
196  AHB1,
197 #endif
198 #if defined(AHB2_PERIPH_EN)
199  AHB2,
200 #endif
201 #if defined(AHB22_PERIPH_EN)
202  AHB22,
203 #endif
204 #if defined(AHB3_PERIPH_EN)
205  AHB3,
206 #endif
207 #if defined(AHB4_PERIPH_EN)
208  AHB4,
209 #endif
210 #if defined(IOP_PERIPH_EN)
211  IOP,
212 #endif
213  BUS_NUMOF
214 } bus_t;
215 
223 uint32_t periph_apb_clk(bus_t bus);
224 
232 uint32_t periph_timer_clk(bus_t bus);
233 
240 void periph_clk_en(bus_t bus, uint32_t mask);
241 
248 void periph_clk_dis(bus_t bus, uint32_t mask);
249 
256 void periph_lpclk_en(bus_t bus, uint32_t mask);
257 
264 void periph_lpclk_dis(bus_t bus, uint32_t mask);
265 
266 #ifdef __cplusplus
267 }
268 #endif
269 
bus_t
bus_t
On-Chip buses.
Definition: periph_cpu.h:76
APB1
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:78
AHB
@ AHB
Advanced High-performance Bus.
Definition: periph_cpu.h:77
APB2
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:79
periph_apb_clk
uint32_t periph_apb_clk(bus_t bus)
Get the actual bus clock frequency for the APB buses.
periph_lpclk_en
void periph_lpclk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock in low power mode.
periph_clk_en
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
periph_clk_dis
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.
periph_timer_clk
uint32_t periph_timer_clk(bus_t bus)
Get the actual timer clock frequency.
periph_lpclk_dis
void periph_lpclk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock in low power mode.
bus_t
bus_t
CPU specific LSI clock speed.
Definition: cpu_common.h:179
BUS_NUMOF
@ BUS_NUMOF
number of buses
Definition: cpu_common.h:213