periph_cpu_common.h

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/*
 * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once
 
#include "cpu.h"
#include "exti_config.h"
#include "timer_config.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define CPUID_LEN           (16U)
 
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#ifndef MODULE_PERIPH_DMA
#  define PERIPH_SPI_NEEDS_TRANSFER_REG
#  define PERIPH_SPI_NEEDS_TRANSFER_REGS
#endif
#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_READ_REGS
#define PERIPH_I2C_NEED_WRITE_REG
#define PERIPH_I2C_NEED_WRITE_REGS
#define PERIPH_I2C_MAX_BYTES_PER_FRAME 256
 
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
#define GPIO_UNDEF          (0xffffffff)
 
#ifdef MODULE_PERIPH_GPIO_FAST_READ
#  ifdef PORT_IOBUS_SEC
#    define GPIO_PIN(x, y)  (((gpio_t)(&PORT_IOBUS_SEC->Group[x])) | y)
#  else /* Use IOBUS access when available */
#    define GPIO_PIN(x, y)  (((gpio_t)(&PORT_IOBUS->Group[x])) | y)
#  endif /* PORT_IOBUS_SEC */
#else
#  ifdef PORT_SEC
#    define GPIO_PIN(x, y)  (((gpio_t)(&PORT_SEC->Group[x])) | y)
#  else
#    define GPIO_PIN(x, y)  (((gpio_t)(&PORT->Group[x])) | y)
#  endif /* PORT_IOBUS_SEC */
#endif
 
enum {
    PA = 0,                 
    PB = 1,                 
    PC = 2,                 
    PD = 3,                 
};
 
#define GPIO_MODE(pr, ie, pe)   (pr | (ie << 1) | (pe << 2))
 
#ifndef DOXYGEN
#  define HAVE_GPIO_MODE_T
typedef enum {
    GPIO_IN    = GPIO_MODE(0, 1, 0),    
    GPIO_IN_PD = GPIO_MODE(0, 1, 1),    
    GPIO_IN_PU = GPIO_MODE(1, 1, 1),    
    GPIO_OUT   = GPIO_MODE(0, 0, 0),    
    GPIO_OD    = 0xfe,                  
    GPIO_OD_PU = 0xff                   
} gpio_mode_t;
 
#  define HAVE_GPIO_SLEW_T
typedef enum {
    GPIO_SLEW_SLOWEST = 0,
    GPIO_SLEW_SLOW = 0,
    GPIO_SLEW_FAST = 0,
    GPIO_SLEW_FASTEST = 0,
} gpio_slew_t;
 
#  define HAVE_GPIO_PULL_STRENGTH_T
typedef enum {
    GPIO_PULL_WEAKEST = 0,
    GPIO_PULL_WEAK = 0,
    GPIO_PULL_STRONG = 0,
    GPIO_PULL_STRONGEST = 0
} gpio_pull_strength_t;
 
#  define HAVE_GPIO_DRIVE_STRENGTH_T
typedef enum {
    GPIO_DRIVE_WEAKEST = 0,
    GPIO_DRIVE_WEAK = 0,
    GPIO_DRIVE_STRONG = 1,
    GPIO_DRIVE_STRONGEST = 1
} gpio_drive_strength_t;
 
#  define HAVE_GPIO_PULL_T
typedef enum {
    GPIO_FLOATING,
    GPIO_PULL_UP,
    GPIO_PULL_DOWN,
    GPIO_PULL_KEEP,
} gpio_pull_t;
 
#  define HAVE_GPIO_STATE_T
typedef enum {
    GPIO_OUTPUT_PUSH_PULL,
    GPIO_OUTPUT_OPEN_DRAIN,
    GPIO_OUTPUT_OPEN_SOURCE,
    GPIO_INPUT,
    GPIO_USED_BY_PERIPHERAL,
    GPIO_DISCONNECT,
} gpio_state_t;
 
#  define HAVE_GPIO_IRQ_TRIG_T
typedef enum {
    GPIO_TRIGGER_EDGE_RISING    = EIC_CONFIG_SENSE0_RISE_Val,
    GPIO_TRIGGER_EDGE_FALLING   = EIC_CONFIG_SENSE0_FALL_Val,
    GPIO_TRIGGER_EDGE_BOTH      = EIC_CONFIG_SENSE0_BOTH_Val,
    GPIO_TRIGGER_LEVEL_HIGH     = EIC_CONFIG_SENSE0_HIGH_Val,
    GPIO_TRIGGER_LEVEL_LOW      = EIC_CONFIG_SENSE0_LOW_Val,
} gpio_irq_trig_t;
 
#  define HAVE_GPIO_CONF_T
typedef union gpio_conf_sam0 gpio_conf_t;
 
#  define HAVE_GPIO_FLANK_T
typedef enum {
    GPIO_FALLING = 2,       
    GPIO_RISING = 1,        
    GPIO_BOTH = 3           
} gpio_flank_t;
#endif /* ndef DOXYGEN */
 
union gpio_conf_sam0 {
    uint8_t bits;  
    struct {
        gpio_state_t state                      : 3;
        gpio_pull_t pull                        : 2;
        gpio_drive_strength_t drive_strength    : 1;
        bool initial_value                      : 1;
        uint8_t                                 : 1; 
    };
};
 
#ifndef SAM_MUX_T
typedef enum {
    GPIO_MUX_A = 0x0,       
    GPIO_MUX_B = 0x1,       
    GPIO_MUX_C = 0x2,       
    GPIO_MUX_D = 0x3,       
    GPIO_MUX_E = 0x4,       
    GPIO_MUX_F = 0x5,       
    GPIO_MUX_G = 0x6,       
    GPIO_MUX_H = 0x7,       
    GPIO_MUX_I = 0x8,       
    GPIO_MUX_J = 0x9,       
    GPIO_MUX_K = 0xa,       
    GPIO_MUX_L = 0xb,       
    GPIO_MUX_M = 0xc,       
    GPIO_MUX_N = 0xd,       
    GPIO_MUX_DISABLED = 0xff, 
} gpio_mux_t;
#endif
 
typedef enum {
    UART_PAD_RX_0 = 0x0,    
    UART_PAD_RX_1 = 0x1,    
    UART_PAD_RX_2 = 0x2,    
    UART_PAD_RX_3 = 0x3,    
} uart_rxpad_t;
 
typedef enum {
    UART_PAD_TX_0             = 0x0,    
    UART_PAD_TX_2             = 0x1,    
    UART_PAD_TX_0_RTS_2_CTS_3 = 0x2,    
} uart_txpad_t;
 
typedef enum {
    UART_FLAG_NONE            = 0x0,    
    UART_FLAG_RUN_STANDBY     = 0x1,    
    UART_FLAG_WAKEUP          = 0x2,    
    UART_FLAG_TX_ONDEMAND     = 0x4,    
} uart_flag_t;
 
#ifndef DOXYGEN
#  define HAVE_UART_DATA_BITS_T
typedef enum {
    UART_DATA_BITS_5 = 0x5,   
    UART_DATA_BITS_6 = 0x6,   
    UART_DATA_BITS_7 = 0x7,   
    UART_DATA_BITS_8 = 0x0,   
} uart_data_bits_t;
#  define uart_pin_rx(dev) uart_config[dev].rx_pin
#  define uart_pin_tx(dev) uart_config[dev].tx_pin
#endif /* ndef DOXYGEN */
 
#ifndef UART_TXBUF_SIZE
#  define UART_TXBUF_SIZE  (64)
#endif
 
typedef struct {
    SercomUsart *dev;       
    gpio_t rx_pin;          
    gpio_t tx_pin;          
#ifdef MODULE_PERIPH_UART_HW_FC
    gpio_t rts_pin;          
    gpio_t cts_pin;          
#endif
    gpio_mux_t mux;         
    uart_rxpad_t rx_pad;    
    uart_txpad_t tx_pad;    
    uart_flag_t flags;      
    uint8_t gclk_src;       
} uart_conf_t;
 
enum {
    TIMER_TYPE_TC,          
    TIMER_TYPE_TCC,         
};
 
typedef struct {
    union {
#ifdef REV_TC
        Tc *tc;                 
#endif
#ifdef REV_TCC
        Tcc *tcc;               
#endif
    } dev;                      
#ifdef MCLK
    volatile uint32_t *mclk;    
    uint32_t mclk_mask;         
#else
    uint32_t pm_mask;           
#endif
    uint16_t gclk_id;           
    uint8_t type;               
} tc_tcc_cfg_t;
 
#ifdef MCLK
#  define TC_CONFIG(tim)                  { \
        .dev       = {.tc = tim},           \
        .mclk      = MCLK_ ## tim,          \
        .mclk_mask = MCLK_ ## tim ## _MASK, \
        .gclk_id   = tim ## _GCLK_ID,       \
        .type      = TIMER_TYPE_TC,       }
#else
#  define TC_CONFIG(tim)                  { \
        .dev       = {.tc = tim},           \
        .pm_mask   = PM_APBCMASK_ ## tim,   \
        .gclk_id   = tim ## _GCLK_ID,       \
        .type      = TIMER_TYPE_TC,       }
#endif
 
#ifdef MCLK
#  define TCC_CONFIG(tim)                 { \
        .dev       = {.tcc = tim},          \
        .mclk      = MCLK_ ## tim,          \
        .mclk_mask = MCLK_ ## tim ## _MASK, \
        .gclk_id   = tim ## _GCLK_ID,       \
        .type      = TIMER_TYPE_TCC,      }
#else
#  define TCC_CONFIG(tim)                 { \
        .dev       = {.tcc = tim},          \
        .pm_mask   = PM_APBCMASK_ ## tim,   \
        .gclk_id   = tim ## _GCLK_ID,       \
        .type      = TIMER_TYPE_TCC,      }
#endif
 
typedef struct {
    gpio_t pin;             
    gpio_mux_t mux;         
    uint8_t chan;           
} pwm_conf_chan_t;
 
typedef struct {
    tc_tcc_cfg_t tim;               
    const pwm_conf_chan_t *chan;    
    uint8_t chan_numof;             
    uint8_t gclk_src;               
} pwm_conf_t;
 
typedef enum {
    SPI_PAD_MISO_0 = 0x0,       
    SPI_PAD_MISO_1 = 0x1,       
    SPI_PAD_MISO_2 = 0x2,       
    SPI_PAD_MISO_3 = 0x3,       
} spi_misopad_t;
 
typedef enum {
    SPI_PAD_MOSI_0_SCK_1 = 0x0, 
    SPI_PAD_MOSI_2_SCK_3 = 0x1, 
    SPI_PAD_MOSI_3_SCK_1 = 0x2, 
    SPI_PAD_MOSI_0_SCK_3 = 0x3, 
} spi_mosipad_t;
 
#ifndef DOXYGEN
#  define HAVE_SPI_MODE_T
typedef enum {
    SPI_MODE_0 = 0x0,       
    SPI_MODE_1 = 0x1,       
    SPI_MODE_2 = 0x2,       
    SPI_MODE_3 = 0x3        
} spi_mode_t;
#  define HAVE_SPI_CLK_T
typedef enum {
    SPI_CLK_100KHZ =   100000U, 
    SPI_CLK_400KHZ =   400000U, 
    SPI_CLK_1MHZ   =  1000000U, 
    SPI_CLK_5MHZ   =  5000000U, 
    SPI_CLK_10MHZ  = 10000000U  
} spi_clk_t;
#  define spi_pin_mosi(dev) spi_config[dev].mosi_pin
#  define spi_pin_miso(dev) spi_config[dev].miso_pin
#  define spi_pin_clk(dev)  spi_config[dev].clk_pin
#endif /* ndef DOXYGEN */
 
typedef struct {
    void *dev;              
    gpio_t miso_pin;        
    gpio_t mosi_pin;        
    gpio_t clk_pin;         
    gpio_mux_t miso_mux;    
    gpio_mux_t mosi_mux;    
    gpio_mux_t clk_mux;     
    spi_misopad_t miso_pad; 
    spi_mosipad_t mosi_pad; 
    uint8_t gclk_src;       
#ifdef MODULE_PERIPH_DMA
    uint8_t tx_trigger;     
    uint8_t rx_trigger;     
#endif
} spi_conf_t;
typedef enum {
    I2C_FLAG_NONE            = 0x0,    
    I2C_FLAG_RUN_STANDBY     = 0x1,    
} i2c_flag_t;
 
#ifndef DOXYGEN
#  define HAVE_I2C_SPEED_T
typedef enum {
    I2C_SPEED_LOW       = 10000U,      
    I2C_SPEED_NORMAL    = 100000U,     
    I2C_SPEED_FAST      = 400000U,     
    I2C_SPEED_FAST_PLUS = 1000000U,    
    I2C_SPEED_HIGH      = 3400000U,    
} i2c_speed_t;
#  define i2c_pin_sda(dev) i2c_config[dev].sda_pin
#  define i2c_pin_scl(dev) i2c_config[dev].scl_pin
#endif /* ndef DOXYGEN */
 
typedef struct {
    SercomI2cm *dev;        
    i2c_speed_t speed;      
    gpio_t scl_pin;         
    gpio_t sda_pin;         
    gpio_mux_t mux;         
    uint8_t gclk_src;       
    uint8_t flags;          
} i2c_conf_t;
 
typedef struct {
    Tc *dev;                
    IRQn_Type irq;          
#ifdef MCLK
    volatile uint32_t *mclk;
    uint32_t mclk_mask;     
    uint16_t gclk_id;       
#else
    uint32_t pm_mask;       
    uint16_t gclk_ctrl;     
#endif
    uint8_t gclk_src;       
    uint16_t flags;         
} tc32_conf_t;
 
#define TIMER_CHANNEL_NUMOF (2)
 
void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
 
#ifdef PM_SLEEPCFG_SLEEPMODE_OFF
 
#  define PROVIDES_PM_OFF
 
#  define PROVIDES_PM_LAYERED_OFF
 
#endif /* PM_SLEEPCFG_SLEEPMODE_OFF */
 
void gpio_pm_cb_enter(int deep);
 
void gpio_pm_cb_leave(int deep);
 
void cpu_pm_cb_enter(int deep);
 
void cpu_pm_cb_leave(int deep);
 
static inline void sam0_cortexm_sleep(int deep)
{
#ifdef MODULE_PERIPH_GPIO
    gpio_pm_cb_enter(deep);
#endif
 
    cpu_pm_cb_enter(deep);
 
    cortexm_sleep(deep);
 
    cpu_pm_cb_leave(deep);
 
#ifdef MODULE_PERIPH_GPIO
    gpio_pm_cb_leave(deep);
#endif
}
 
void gpio_disable_mux(gpio_t pin);
 
typedef enum {
    SAM0_VREG_LDO,  
    SAM0_VREG_BUCK  
} sam0_supc_t;
 
static inline void sam0_set_voltage_regulator(sam0_supc_t src)
{
#ifdef REG_SUPC_VREG
    if (src == SAM0_VREG_BUCK) {
        SUPC->VREG.reg |= (1 << SUPC_VREG_SEL_Pos);
    }
    else {
        SUPC->VREG.reg &= ~(1 << SUPC_VREG_SEL_Pos);
    }
    while (!(SUPC->STATUS.reg & SUPC_STATUS_VREGRDY)) {}
#else
    (void) src;
    assert(0);
#endif
}
 
uint32_t sam0_gclk_freq(uint8_t id);
 
void sam0_gclk_enable(uint8_t id);
 
static inline uint8_t sercom_id(const void *sercom)
{
#ifdef SERCOM0
    if (sercom == SERCOM0) {
        return 0;
    }
#endif
#ifdef SERCOM1
    if (sercom == SERCOM1) {
        return 1;
    }
#endif
#ifdef SERCOM2
    if (sercom == SERCOM2) {
        return 2;
    }
#endif
#ifdef SERCOM3
    if (sercom == SERCOM3) {
        return 3;
    }
#endif
#ifdef SERCOM4
    if (sercom == SERCOM4) {
        return 4;
    }
#endif
#ifdef SERCOM5
    if (sercom == SERCOM5) {
        return 5;
    }
#endif
#ifdef SERCOM6
    if (sercom == SERCOM6) {
        return 6;
    }
#endif
#ifdef SERCOM7
    if (sercom == SERCOM7) {
        return 7;
    }
#endif
 
    /* should not be reached, so fail with assert */
    assert(false);
 
    return SERCOM_INST_NUM;
}
 
static inline void sercom_clk_en(void *sercom)
{
    const uint8_t id = sercom_id(sercom);
#if defined(CPU_COMMON_SAMD21)
    PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << id);
#elif defined (CPU_COMMON_SAMD5X)
    if (id < 2) {
        MCLK->APBAMASK.reg |= (1 << (id + 12));
    } else if (id < 4) {
        MCLK->APBBMASK.reg |= (1 << (id + 7));
    } else {
        MCLK->APBDMASK.reg |= (1 << (id - 4));
    }
#else
    if (id < 5) {
        MCLK->APBCMASK.reg |= (MCLK_APBCMASK_SERCOM0 << id);
    }
#  if defined(CPU_COMMON_SAML21)
    else {
        MCLK->APBDMASK.reg |= (MCLK_APBDMASK_SERCOM5);
    }
#  endif /* CPU_COMMON_SAML21 */
#endif
}
 
static inline void sercom_clk_dis(void *sercom)
{
    const uint8_t id = sercom_id(sercom);
#if defined(CPU_COMMON_SAMD21)
    PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << id);
#elif defined (CPU_COMMON_SAMD5X)
    if (id < 2) {
        MCLK->APBAMASK.reg &= ~(1 << (id + 12));
    } else if (id < 4) {
        MCLK->APBBMASK.reg &= ~(1 << (id + 7));
    } else {
        MCLK->APBDMASK.reg &= ~(1 << (id - 4));
    }
#else
    if (id < 5) {
        MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << id);
    }
#  if defined (CPU_COMMON_SAML21)
    else {
        MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_SERCOM5);
    }
#  endif /* CPU_COMMON_SAML21 */
#endif
}
 
#ifdef CPU_COMMON_SAMD5X
static inline uint8_t _sercom_gclk_id_core(uint8_t sercom_id) {
    if (sercom_id < 2) {
        return sercom_id + 7;
    }
    else if (sercom_id < 4) {
        return sercom_id + 21;
    }
    else {
        return sercom_id + 30;
    }
}
#endif
 
static inline void sercom_set_gen(void *sercom, uint8_t gclk)
{
    const uint8_t id = sercom_id(sercom);
    sam0_gclk_enable(gclk);
#if defined(CPU_COMMON_SAMD21)
    GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(gclk) |
                         (SERCOM0_GCLK_ID_CORE + id));
    while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
#elif defined(CPU_COMMON_SAMD5X)
    GCLK->PCHCTRL[_sercom_gclk_id_core(id)].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
#else
    if (id < 5) {
        GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + id].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
    }
#  if defined(CPU_COMMON_SAML21)
    else {
        GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
    }
#  endif /* CPU_COMMON_SAML21 */
#endif
}
 
static inline bool cpu_woke_from_backup(void)
{
#ifdef RSTC_RCAUSE_BACKUP
    return RSTC->RCAUSE.reg & RSTC_RCAUSE_BACKUP;
#else
    return false;
#endif
}
 
typedef struct {
    uint32_t inputctrl;     
#ifdef ADC0
    Adc *dev;               
#endif
} adc_conf_chan_t;
 
#ifndef ADC_INPUTCTRL_DIFFMODE
#  define ADC_INPUTCTRL_DIFFMODE    (1 << 7)
#endif
 
#define ADC_REFSEL_AREFA_PIN    GPIO_PIN(PA, 3)
 
#define ADC_REFSEL_AREFB_PIN    GPIO_PIN(PA, 4)
 
#if defined(ADC_REFCTRL_REFSEL_AREFC) || DOXYGEN
#  define ADC_REFSEL_AREFC_PIN  GPIO_PIN(PA, 6)
#endif
 
#ifndef DOXYGEN
#  define HAVE_ADC_RES_T
typedef enum {
    ADC_RES_6BIT  = 0xff,                       
#  if defined(ADC_CTRLB_RESSEL)
    ADC_RES_8BIT  = ADC_CTRLB_RESSEL_8BIT_Val,  
    ADC_RES_10BIT = ADC_CTRLB_RESSEL_10BIT_Val, 
    ADC_RES_12BIT = ADC_CTRLB_RESSEL_12BIT_Val, 
#  elif defined(ADC_CTRLC_RESSEL)
    ADC_RES_8BIT  = ADC_CTRLC_RESSEL_8BIT_Val,  
    ADC_RES_10BIT = ADC_CTRLC_RESSEL_10BIT_Val, 
    ADC_RES_12BIT = ADC_CTRLC_RESSEL_12BIT_Val, 
#  endif
    ADC_RES_16BIT_2SAMPL    = ( 0x1 << 2) | 0x1, 
    ADC_RES_16BIT_4SAMPL    = ( 0x2 << 2) | 0x1, 
    ADC_RES_16BIT_8SAMPL    = ( 0x3 << 2) | 0x1, 
    ADC_RES_16BIT_16SAMPL   = ( 0x4 << 2) | 0x1, 
    ADC_RES_16BIT_32SAMPL   = ( 0x5 << 2) | 0x1, 
    ADC_RES_16BIT_64SAMPL   = ( 0x6 << 2) | 0x1, 
    ADC_RES_16BIT_128SAMPL  = ( 0x7 << 2) | 0x1, 
    ADC_RES_16BIT_256SAMPL  = ( 0x8 << 2) | 0x1, 
    ADC_RES_16BIT_512SAMPL  = ( 0x9 << 2) | 0x1, 
    ADC_RES_16BIT_1024SAMPL = ( 0xA << 2) | 0x1, 
    ADC_RES_14BIT = 0xfe,                        
} adc_res_t;
 
#  define ADC_RES_16BIT ADC_RES_16BIT_16SAMPL   
#endif /* DOXYGEN */
 
#ifndef ETH_RX_BUFFER_COUNT
#  define ETH_RX_BUFFER_COUNT (4)
#endif
 
#ifndef ETH_TX_BUFFER_COUNT
#  define ETH_TX_BUFFER_COUNT (2)
#endif
 
#ifndef ETH_RX_BUFFER_SIZE
#  define ETH_RX_BUFFER_SIZE (1536)
#endif
 
#ifndef ETH_TX_BUFFER_SIZE
#  define ETH_TX_BUFFER_SIZE (1536)
#endif
#if defined(GMAC_INST_NUM) || defined(DOXYGEN)
typedef struct {
    Gmac *dev;                
    gpio_t refclk;            
    gpio_t txen;              
    gpio_t txd0;              
    gpio_t txd1;              
    gpio_t crsdv;             
    gpio_t rxd0;              
    gpio_t rxd1;              
    gpio_t rxer;              
    gpio_t mdc;               
    gpio_t mdio;              
    gpio_t rst_pin;           
    gpio_t int_pin;           
} sam0_common_gmac_config_t;
#endif
 
#define USBDEV_CPU_DMA_ALIGNMENT       (4)
 
#define USBDEV_CPU_DMA_REQUIREMENTS    __attribute__((aligned(USBDEV_CPU_DMA_ALIGNMENT)))
 
#if defined(USB_INST_NUM) || defined(DOXYGEN)
typedef struct {
    gpio_t dm;              
    gpio_t dp;              
    gpio_mux_t d_mux;       
    UsbDevice *device;      
    uint8_t gclk_src;       
} sam0_common_usb_config_t;
#endif /* USB_INST_NUM */
 
#define SDMMC_CPU_DMA_ALIGNMENT     4
 
#define SDMMC_CPU_DMA_REQUIREMENTS  __attribute__((aligned(SDMMC_CPU_DMA_ALIGNMENT)))
 
typedef struct {
    void *sdhc; 
    gpio_t cd;  
    gpio_t wp;  
} sdhc_conf_t;
 
/* Limits are in clock cycles according to data sheet.
   As the WDT is clocked by a 1024 Hz clock, 1 cycle ≈ 1 ms */
#define NWDT_TIME_LOWER_LIMIT          (8U)
#define NWDT_TIME_UPPER_LIMIT          (16384U)
#define WDT_HAS_STOP                   (1)
#define WDT_HAS_INIT                   (1)
 
typedef struct {
    gpio_t pin;             
    uint8_t gclk_src;       
} freqm_config_t;
 
#if defined(REV_DMAC) || DOXYGEN
#  define DMA_TRIGGER_DISABLED         0
 
#  if defined(CPU_COMMON_SAML21) || defined(DOXYGEN)
#    define DMA_DESCRIPTOR_IN_LPSRAM
#  endif
 
#  ifdef DMA_DESCRIPTOR_IN_LPSRAM
#    define DMA_DESCRIPTOR_ATTRS    __attribute__((section(".backup.bss")))
#  else
#    define DMA_DESCRIPTOR_ATTRS
#  endif
 
typedef unsigned dma_t;
 
typedef enum {
    DMA_INCR_NONE   = 0,    
    DMA_INCR_SRC    = 1,    
    DMA_INCR_DEST   = 2,    
    DMA_INCR_BOTH   = 3,    
} dma_incr_t;
 
void dma_init(void);
 
dma_t dma_acquire_channel(void);
 
void dma_release_channel(dma_t dma);
 
void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq);
 
void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst,
                 size_t num, dma_incr_t incr);
 
void dma_prepare_src(dma_t dma, const void *src, size_t num, bool incr);
 
void dma_prepare_dst(dma_t dma, void *dst, size_t num, bool incr);
 
void dma_append(dma_t dma, DmacDescriptor *descriptor, uint8_t width,
                const void *src, void *dst, size_t num, dma_incr_t incr);
 
void dma_append_src(dma_t dma, DmacDescriptor *next, const void *src,
                    size_t num, bool incr);
 
void dma_append_dst(dma_t dma, DmacDescriptor *next, void *dst, size_t num,
                    bool incr);
 
void dma_start(dma_t dma);
 
void dma_wait(dma_t dma);
 
void dma_cancel(dma_t dma);
#endif /* REV_DMAC || DOXYGEN */
 
void rtc_tamper_init(void);
 
int rtc_tamper_register(gpio_t pin, gpio_flank_t flank);
 
void rtc_tamper_enable(void);
 
uint8_t rtc_get_tamper_event(void);
 
uint8_t rtc_tamper_pin_mask(gpio_t pin);
typedef struct sam0_aux_cfg_mapping nvm_user_page_t;
 
#ifdef FLASH_USER_PAGE_SIZE
#  define FLASH_USER_PAGE_AUX_SIZE (FLASH_USER_PAGE_SIZE - sizeof(nvm_user_page_t))
#else
#  define FLASH_USER_PAGE_AUX_SIZE (AUX_PAGE_SIZE * AUX_NB_OF_PAGES - sizeof(nvm_user_page_t))
#endif
 
void sam0_flashpage_aux_reset(const nvm_user_page_t *cfg);
 
void sam0_flashpage_aux_write(uint32_t offset, const void *data, size_t len);
 
#define sam0_flashpage_aux_get(offset)  \
    (const void*)((uint8_t*)NVMCTRL_USER + sizeof(nvm_user_page_t) + (offset))
 
#define sam0_flashpage_aux_cfg() \
    ((const nvm_user_page_t*)NVMCTRL_USER)
 
#ifdef __cplusplus
}
#endif