cfg_timer_default.h
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1 /*
2  * SPDX-FileCopyrightText: 2016 Kees Bakker, SODAQ
3  * SPDX-License-Identifier: LGPL-2.1-only
4  */
5 
6 #pragma once
7 
18 #include <stdint.h>
19 
20 #include "cpu.h"
21 #include "periph_cpu.h"
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
31 static const tc32_conf_t timer_config[] = {
32  { /* Timer 0 - System Clock */
33  .dev = TC3,
34  .irq = TC3_IRQn,
35  .pm_mask = PM_APBCMASK_TC3,
36  .gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
37 #if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
38  .gclk_src = SAM0_GCLK_1MHZ,
39 #else
40  .gclk_src = SAM0_GCLK_MAIN,
41 #endif
42  .flags = TC_CTRLA_MODE_COUNT16,
43  },
44  { /* Timer 1 */
45  .dev = TC4,
46  .irq = TC4_IRQn,
47  .pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
48  .gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
49 #if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
50  .gclk_src = SAM0_GCLK_1MHZ,
51 #else
52  .gclk_src = SAM0_GCLK_MAIN,
53 #endif
54  .flags = TC_CTRLA_MODE_COUNT32,
55  }
56 };
57 
58 #define TIMER_0_MAX_VALUE 0xffff
59 
60 /* interrupt function name mapping */
61 #define TIMER_0_ISR isr_tc3
62 #define TIMER_1_ISR isr_tc4
63 
64 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
67 #ifdef __cplusplus
68 }
69 #endif
70 
timer_config
static const timer_conf_t timer_config[]
Configuration of the exposed timers.
Definition: cfg_timer_default.h:36
SAM0_GCLK_1MHZ
@ SAM0_GCLK_1MHZ
1 MHz clock for xTimer
Definition: periph_cpu.h:72
SAM0_GCLK_MAIN
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition: periph_cpu.h:70
tc32_conf_t
Timer device configuration.
Definition: periph_cpu_common.h:570
timer_conf_t::dev
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:261