periph_conf.h
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1 /*
2  * Copyright (C) 2019 Benjamin Valentin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 /* This board provides an LSE */
26 #ifndef CONFIG_BOARD_HAS_LSE
27 #define CONFIG_BOARD_HAS_LSE 1
28 #endif
29 
30 /* This board provides an HSE */
31 #ifndef CONFIG_BOARD_HAS_HSE
32 #define CONFIG_BOARD_HAS_HSE 1
33 #endif
34 
35 /* The HSE provides a 25MHz clock */
36 #ifndef CONFIG_CLOCK_HSE
37 #define CONFIG_CLOCK_HSE MHZ(25)
38 #endif
39 
40 #include "clk_conf.h"
41 #include "cfg_i2c1_pb8_pb9.h"
42 #include "cfg_timer_tim5.h"
43 #include "cfg_usb_otg_fs.h"
44 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
53 static const uart_conf_t uart_config[] = {
54  {
55  .dev = USART2,
56  .rcc_mask = RCC_APB1ENR_USART2EN,
57  .rx_pin = GPIO_PIN(PORT_A, 3),
58  .tx_pin = GPIO_PIN(PORT_A, 2),
59  .rx_af = GPIO_AF7,
60  .tx_af = GPIO_AF7,
61  .bus = APB1,
62  .irqn = USART2_IRQn,
63 #ifdef MODULE_PERIPH_DMA
64  .dma = DMA_STREAM_UNDEF,
65  .dma_chan = UINT8_MAX,
66 #endif
67  },
68  {
69  .dev = USART1,
70  .rcc_mask = RCC_APB2ENR_USART1EN,
71  .rx_pin = GPIO_PIN(PORT_A, 10),
72  .tx_pin = GPIO_PIN(PORT_A, 9),
73  .rx_af = GPIO_AF7,
74  .tx_af = GPIO_AF7,
75  .bus = APB2,
76  .irqn = USART1_IRQn,
77 #ifdef MODULE_PERIPH_DMA
78  .dma = DMA_STREAM_UNDEF,
79  .dma_chan = UINT8_MAX,
80 #endif
81  },
82 };
83 
84 /* assign ISR vector names */
85 #define UART_0_ISR isr_usart2
86 #define UART_1_ISR isr_usart1
87 
88 /* deduct number of defined UART interfaces */
89 #define UART_NUMOF ARRAY_SIZE(uart_config)
95 static const pwm_conf_t pwm_config[] = {
96  {
97  .dev = TIM2,
98  .rcc_mask = RCC_APB1ENR_TIM2EN,
99  .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0 },
100  { .pin = GPIO_PIN(PORT_B, 3), /* D3 */ .cc_chan = 1 },
101  { .pin = GPIO_PIN(PORT_B, 10), /* D6 */ .cc_chan = 2 },
102  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
103  .af = GPIO_AF1,
104  .bus = APB1
105  },
106  {
107  .dev = TIM3,
108  .rcc_mask = RCC_APB1ENR_TIM3EN,
109  .chan = { { .pin = GPIO_PIN(PORT_B, 4), /* D5 */ .cc_chan = 0 },
110  { .pin = GPIO_PIN(PORT_C, 7), /* D9 */ .cc_chan = 1 },
111  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
112  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
113  .af = GPIO_AF2,
114  .bus = APB1
115  },
116 };
117 
118 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
125 static const spi_conf_t spi_config[] = {
126  { /* U3 - SPI flash */
127  .dev = SPI1,
128  .mosi_pin = GPIO_PIN(PORT_A, 7),
129  .miso_pin = GPIO_PIN(PORT_A, 6),
130  .sclk_pin = GPIO_PIN(PORT_A, 5),
131  .cs_pin = GPIO_PIN(PORT_A, 4),
132  .mosi_af = GPIO_AF5,
133  .miso_af = GPIO_AF5,
134  .sclk_af = GPIO_AF5,
135  .cs_af = GPIO_AF5,
136  .rccmask = RCC_APB2ENR_SPI1EN,
137  .apbbus = APB2
138  },
139  {
140  .dev = SPI2,
141  .mosi_pin = GPIO_PIN(PORT_B, 15),
142  .miso_pin = GPIO_PIN(PORT_B, 14),
143  .sclk_pin = GPIO_PIN(PORT_B, 13),
144  .cs_pin = GPIO_PIN(PORT_B, 12),
145  .mosi_af = GPIO_AF5,
146  .miso_af = GPIO_AF5,
147  .sclk_af = GPIO_AF5,
148  .cs_af = GPIO_AF5,
149  .rccmask = RCC_APB1ENR_SPI2EN,
150  .apbbus = APB1
151  },
152  {
153  .dev = SPI3,
154  .mosi_pin = GPIO_PIN(PORT_B, 5),
155  .miso_pin = GPIO_PIN(PORT_B, 4),
156  .sclk_pin = GPIO_PIN(PORT_B, 3),
157  .cs_pin = GPIO_PIN(PORT_A, 15),
158  .mosi_af = GPIO_AF6,
159  .miso_af = GPIO_AF6,
160  .sclk_af = GPIO_AF6,
161  .cs_af = GPIO_AF6,
162  .rccmask = RCC_APB1ENR_SPI3EN,
163  .apbbus = APB1
164  },
165 };
166 
167 #define SPI_NUMOF ARRAY_SIZE(spi_config)
179 static const adc_conf_t adc_config[] = {
180  {GPIO_PIN(PORT_A, 0), 0, 0},
181  {GPIO_PIN(PORT_A, 1), 0, 1},
182  {GPIO_PIN(PORT_A, 4), 0, 4},
183  {GPIO_PIN(PORT_B, 0), 0, 8},
184  {GPIO_UNDEF, 0, 18} /* VBAT */
185 };
186 
187 #define VBAT_ADC ADC_LINE(4)
188 #define ADC_NUMOF ARRAY_SIZE(adc_config)
191 #ifdef __cplusplus
192 }
193 #endif
194 
195 #endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition: periph_cpu.h:48
@ PORT_C
port C
Definition: periph_cpu.h:49
@ PORT_A
port A
Definition: periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:97
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:251
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:222
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM5.
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:103
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:107
@ GPIO_AF6
use alternate function 6
Definition: cpu_gpio.h:108
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:109
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:80
ADC device configuration.
Definition: periph_cpu.h:379
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219