periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2017 Eistec AB
3  * 2021-2023 Hugues Larrive
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C"
28 {
29 #endif
30 
35 static const clock_config_t clock_config = {
36  /*
37  * This configuration results in the system running from the FLL output with
38  * the following clock frequencies:
39  * Core: 60 MHz
40  * Bus: 30 MHz
41  * Flex: 20 MHz
42  * Flash: 20 MHz
43  */
44  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) |
45  SIM_CLKDIV1_OUTDIV3(2) | SIM_CLKDIV1_OUTDIV4(2),
46  .rtc_clc = 0, /* External load caps on the FRDM-K22F board */
47  .osc32ksel = SIM_SOPT1_OSC32KSEL(2),
48  .clock_flags =
49  KINETIS_CLOCK_OSC0_EN |
50  KINETIS_CLOCK_RTCOSC_EN |
51  KINETIS_CLOCK_USE_FAST_IRC |
52  0,
53  .default_mode = KINETIS_MCG_MODE_FEE,
54  /* The crystal connected to OSC0 is 8 MHz */
55  .erc_range = KINETIS_MCG_ERC_RANGE_HIGH,
56  .osc_clc = 0, /* External load caps on the FRDM-K22F board */
57  .oscsel = MCG_C7_OSCSEL(0), /* Use OSC0 for external clock */
58  .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
59  .fll_frdiv = MCG_C1_FRDIV(0b011), /* Divide by 256 */
60  .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FLL freq = 48 MHz */
61  .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1920, /* FLL freq = 60 MHz */
62  .pll_prdiv = MCG_C5_PRDIV0(0b00011), /* Divide by 4 */
63  .pll_vdiv = MCG_C6_VDIV0(0b00110), /* Multiply by 30 => PLL freq = 60 MHz */
64 };
65 #define CLOCK_CORECLOCK (60000000ul)
66 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
73 #define PIT_NUMOF (2U)
74 #define PIT_CONFIG { \
75  { \
76  .prescaler_ch = 0, \
77  .count_ch = 1, \
78  }, \
79  { \
80  .prescaler_ch = 2, \
81  .count_ch = 3, \
82  }, \
83 }
84 #define LPTMR_NUMOF (1U)
85 #define LPTMR_CONFIG { \
86  { \
87  .dev = LPTMR0, \
88  .irqn = LPTMR0_IRQn, \
89  .src = 2, \
90  .base_freq = 32768u, \
91  }, \
92 }
93 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
94 
95 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
96 #define PIT_ISR_0 isr_pit1
97 #define PIT_ISR_1 isr_pit3
98 #define LPTMR_ISR_0 isr_lptmr0
105 static const uart_conf_t uart_config[] = {
106  {
107  .dev = UART1,
108  .freq = CLOCK_CORECLOCK,
109  .pin_rx = GPIO_PIN(PORT_E, 1),
110  .pin_tx = GPIO_PIN(PORT_E, 0),
111  .pcr_rx = PORT_PCR_MUX(3),
112  .pcr_tx = PORT_PCR_MUX(3),
113  .irqn = UART1_RX_TX_IRQn,
114  .scgc_addr = &SIM->SCGC4,
115  .scgc_bit = SIM_SCGC4_UART1_SHIFT,
116  .mode = UART_MODE_8N1,
117  .type = KINETIS_UART,
118  },
119  {
120  .dev = UART0,
121  .freq = CLOCK_CORECLOCK,
122  .pin_rx = GPIO_PIN(PORT_D, 6),
123  .pin_tx = GPIO_PIN(PORT_D, 7),
124  .pcr_rx = PORT_PCR_MUX(3),
125  .pcr_tx = PORT_PCR_MUX(3),
126  .irqn = UART0_RX_TX_IRQn,
127  .scgc_addr = &SIM->SCGC4,
128  .scgc_bit = SIM_SCGC4_UART0_SHIFT,
129  .mode = UART_MODE_8N1,
130  .type = KINETIS_UART,
131  },
132 };
133 
134 #define UART_0_ISR (isr_uart1_rx_tx)
135 #define UART_1_ISR (isr_uart0_rx_tx)
136 
137 #define UART_NUMOF ARRAY_SIZE(uart_config)
144 static const adc_conf_t adc_config[] = {
145  /* dev, pin, channel */
146  [0] = { /* ADC0_DP0 */
147  .dev = ADC0, .pin = GPIO_UNDEF,
148  .chan = 0, .avg = ADC_AVG_MAX
149  },
150  [1] = { /* ADC0_DM0 */
151  .dev = ADC0, .pin = GPIO_UNDEF,
152  .chan = 19, .avg = ADC_AVG_MAX
153  },
154  [2] = { /* ADC1_DP0 */
155  .dev = ADC1, .pin = GPIO_UNDEF,
156  .chan = 0, .avg = ADC_AVG_MAX
157  },
158  [3] = { /* ADC1_DM0 */
159  .dev = ADC1, .pin = GPIO_UNDEF,
160  .chan = 19, .avg = ADC_AVG_MAX
161  },
162  [4] = { /* PTB0 (Arduino A0) */
163  .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0),
164  .chan = 8, .avg = ADC_AVG_MAX
165  },
166  [5] = { /* PTB1 (Arduino A1) */
167  .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1),
168  .chan = 9, .avg = ADC_AVG_MAX
169  },
170  [6] = { /* PTC1 (Arduino A2) */
171  .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1),
172  .chan = 15, .avg = ADC_AVG_MAX
173  },
174  [7] = { /* PTC2 (Arduino A3) */
175  .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2),
176  .chan = 4, .avg = ADC_AVG_MAX
177  },
178  /* internal: temperature sensor */
179  /* The temperature sensor has a very high output impedance, it must
180  * not be sampled using hardware averaging, or the sampled values
181  * will be garbage */
182  [8] = {
183  .dev = ADC0, .pin = GPIO_UNDEF,
184  .chan = 26, .avg = ADC_AVG_NONE
185  },
186  /* internal: band gap */
187  /* Note: the band gap buffer uses a bit of current and is turned off
188  * by default, set PMC->REGSC |= PMC_REGSC_BGBE_MASK before reading
189  * or the input will be floating */
190  [9] = {
191  .dev = ADC0, .pin = GPIO_UNDEF,
192  .chan = 27, .avg = ADC_AVG_MAX
193  },
194 };
195 
196 #define ADC_NUMOF ARRAY_SIZE(adc_config)
197 /*
198  * K22F ADC reference settings:
199  * 0: VREFH/VREFL external pin pair
200  * 1: VREF_OUT internal 1.2 V reference (VREF module must be enabled)
201  * 2-3: reserved
202  */
203 #define ADC_REF_SETTING 0
210 static const pwm_conf_t pwm_config[] = {
211  {
212  .ftm = FTM0,
213  .chan = {
214  { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 6 },
215  { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
216  { .pin = GPIO_PIN(PORT_D, 5), .af = 4, .ftm_chan = 5 },
217  },
218  .chan_numof = 3,
219  .ftm_num = 0
220  }
221 };
222 
223 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
236 static const uint32_t spi_clk_config[] = {
237  (
238  SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
239  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
240  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
241  SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
242  ),
243  (
244  SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
245  SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
246  SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
247  SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
248  ),
249  (
250  SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
251  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
252  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
253  SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
254  ),
255  (
256  SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
257  SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
258  SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
259  SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
260  ),
261  (
262  SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
263  SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
264  SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
265  SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
266  )
267 };
268 
269 static const spi_conf_t spi_config[] = {
270  {
271  .dev = SPI0,
272  .pin_miso = GPIO_PIN(PORT_D, 3),
273  .pin_mosi = GPIO_PIN(PORT_D, 2),
274  .pin_clk = GPIO_PIN(PORT_D, 1),
275  .pin_cs = {
276  GPIO_PIN(PORT_C, 4),
277  GPIO_PIN(PORT_D, 4),
278  SPI_CS_UNDEF,
279  SPI_CS_UNDEF,
281  },
282  .pcr = GPIO_AF_2,
283  .simmask = SIM_SCGC6_SPI0_MASK
284  }
285 };
286 
287 #define SPI_NUMOF ARRAY_SIZE(spi_config)
294 static const i2c_conf_t i2c_config[] = {
295  {
296  .i2c = I2C0,
297  .scl_pin = GPIO_PIN(PORT_B, 2),
298  .sda_pin = GPIO_PIN(PORT_B, 3),
299  .freq = CLOCK_BUSCLOCK,
300  .speed = I2C_SPEED_FAST,
301  .irqn = I2C0_IRQn,
302  .scl_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
303  .sda_pcr = (PORT_PCR_MUX(2) | PORT_PCR_ODE_MASK),
304  },
305 };
306 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
307 #define I2C_0_ISR (isr_i2c0)
308 #define I2C_1_ISR (isr_i2c1)
311 #ifdef __cplusplus
312 }
313 #endif
314 
315 #endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition: periph_cpu.h:48
@ PORT_C
port C
Definition: periph_cpu.h:49
@ PORT_E
port E
Definition: periph_cpu.h:51
@ PORT_A
port A
Definition: periph_cpu.h:47
@ PORT_D
port D
Definition: periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:97
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:69
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:251
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:222
static const spi_clk_conf_t spi_clk_config[]
Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
Definition: periph_cpu.h:282
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:363
#define UART0
UART0 register bank.
#define UART1
UART1 register bank.
#define CLOCK_BUSCLOCK
Bus clock frequency, used by several hardware modules in Kinetis CPUs.
Definition: mcg.h:147
#define CLOCK_CORECLOCK
System core clock in Hz.
Definition: periph_conf.h:34
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition: periph_cpu.h:279
#define ADC_AVG_NONE
Disable hardware averaging.
Definition: periph_cpu.h:370
@ KINETIS_UART
Kinetis UART module type.
Definition: periph_cpu.h:538
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition: periph_cpu.h:294
#define ADC_AVG_MAX
Maximum hardware averaging (32 samples)
Definition: periph_cpu.h:374
ADC device configuration.
Definition: periph_cpu.h:379
ADC_TypeDef * dev
ADC device used.
Definition: periph_cpu.h:380
I2C configuration structure.
Definition: periph_cpu.h:299
I2C_Type * i2c
Pointer to hardware module registers.
Definition: periph_cpu.h:459
gpio_t pin
GPIO pin mapped to this channel.
Definition: periph_cpu.h:470
PWM device configuration.
pwm_chan_t chan[TIMER_CHANNEL_NUMOF]
channel mapping set to {GPIO_UNDEF, 0} if not used
Definition: periph_cpu.h:483
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219