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periph_conf.h
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1 /*
2  * Copyright (C) 2015 TriaGnoSys GmbH
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* This board provides an LSE */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 /* This board provides an HSE */
28 #ifndef CONFIG_BOARD_HAS_HSE
29 #define CONFIG_BOARD_HAS_HSE 1
30 #endif
31 
32 #include "periph_cpu.h"
33 #include "clk_conf.h"
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
43 static const timer_conf_t timer_config[] = {
44  {
45  .dev = TIM2,
46  .max = 0x0000ffff,
47  .rcc_mask = RCC_APB1ENR_TIM2EN,
48  .bus = APB1,
49  .irqn = TIM2_IRQn
50  },
51  {
52  .dev = TIM3,
53  .max = 0x0000ffff,
54  .rcc_mask = RCC_APB1ENR_TIM3EN,
55  .bus = APB1,
56  .irqn = TIM3_IRQn
57  }
58 };
59 
60 #define TIMER_0_ISR isr_tim2
61 #define TIMER_1_ISR isr_tim3
62 
63 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
70 static const uart_conf_t uart_config[] = {
71  {
72  .dev = USART2,
73  .rcc_mask = RCC_APB1ENR_USART2EN,
74  .rx_pin = GPIO_PIN(PORT_A, 3),
75  .tx_pin = GPIO_PIN(PORT_A, 2),
76  .bus = APB1,
77  .irqn = USART2_IRQn
78  },
79  {
80  .dev = USART1,
81  .rcc_mask = RCC_APB2ENR_USART1EN,
82  .rx_pin = GPIO_PIN(PORT_A, 10),
83  .tx_pin = GPIO_PIN(PORT_A, 9),
84  .bus = APB2,
85  .irqn = USART1_IRQn
86  },
87  {
88  .dev = USART3,
89  .rcc_mask = RCC_APB1ENR_USART3EN,
90  .rx_pin = GPIO_PIN(PORT_B, 11),
91  .tx_pin = GPIO_PIN(PORT_B, 10),
92  .bus = APB1,
93  .irqn = USART3_IRQn
94  }
95 };
96 
97 #define UART_0_ISR (isr_usart2)
98 #define UART_1_ISR (isr_usart1)
99 #define UART_2_ISR (isr_usart3)
100 
101 #define UART_NUMOF ARRAY_SIZE(uart_config)
108 #ifndef RTT_FREQUENCY
109 #define RTT_FREQUENCY (16384) /* in Hz */
110 #endif
118 static const i2c_conf_t i2c_config[] = {
119  {
120  .dev = I2C1,
121  .speed = I2C_SPEED_NORMAL,
122  .scl_pin = GPIO_PIN(PORT_B, 8),
123  .sda_pin = GPIO_PIN(PORT_B, 9),
124  .bus = APB1,
125  .rcc_mask = RCC_APB1ENR_I2C1EN,
126  .clk = CLOCK_APB1,
127  .irqn = I2C1_EV_IRQn
128  },
129  {
130  .dev = I2C2,
131  .speed = I2C_SPEED_NORMAL,
132  .scl_pin = GPIO_PIN(PORT_B, 10),
133  .sda_pin = GPIO_PIN(PORT_B, 11),
134  .bus = APB1,
135  .rcc_mask = RCC_APB1ENR_I2C2EN,
136  .clk = CLOCK_APB1,
137  .irqn = I2C2_EV_IRQn
138  }
139 };
140 
141 #define I2C_0_ISR isr_i2c1_ev
142 #define I2C_1_ISR isr_i2c2_ev
143 
144 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
151 static const spi_conf_t spi_config[] = {
152  {
153  .dev = SPI1,
154  .mosi_pin = GPIO_PIN(PORT_A, 7),
155  .miso_pin = GPIO_PIN(PORT_A, 6),
156  .sclk_pin = GPIO_PIN(PORT_A, 5),
157  .cs_pin = SPI_CS_UNDEF,
158  .rccmask = RCC_APB2ENR_SPI1EN,
159  .apbbus = APB2
160  },
161  {
162  .dev = SPI2,
163  .mosi_pin = GPIO_PIN(PORT_B, 15),
164  .miso_pin = GPIO_PIN(PORT_B, 14),
165  .sclk_pin = GPIO_PIN(PORT_B, 13),
166  .cs_pin = SPI_CS_UNDEF,
167  .rccmask = RCC_APB1ENR_SPI2EN,
168  .apbbus = APB1
169  }
170 };
171 
172 #define SPI_NUMOF ARRAY_SIZE(spi_config)
179 static const adc_conf_t adc_config[] = {
180  { .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 0 }, /* ADC12_IN0 */
181  { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 1 }, /* ADC12_IN1 */
182  { .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 4 }, /* ADC12_IN4 */
183  { .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 8 }, /* ADC12_IN8 */
184  { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 11 }, /* ADC12_IN11 */
185  { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 10 }, /* ADC12_IN10 */
186 };
187 
188 #define ADC_NUMOF ARRAY_SIZE(adc_config)
191 #ifdef __cplusplus
192 }
193 #endif
194 
195 #endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition: periph_cpu.h:48
@ PORT_C
port C
Definition: periph_cpu.h:49
@ PORT_A
port A
Definition: periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:97
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:69
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:40
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:251
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:80
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:278
#define CLOCK_APB1
Half AHB clock.
ADC device configuration.
Definition: periph_cpu.h:379
gpio_t pin
pin connected to the channel
Definition: periph_cpu.h:288
I2C configuration structure.
Definition: periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:300
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338
Timer device configuration.
Definition: periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:265
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219