periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * Copyright (C) 2015 Freie Universität Berlin
4  * Copyright (C) 2015 Hamburg University of Applied Sciences
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef PERIPH_CONF_H
24 #define PERIPH_CONF_H
25 
26 /* This board provides an LSE */
27 #ifndef CONFIG_BOARD_HAS_LSE
28 #define CONFIG_BOARD_HAS_LSE 1
29 #endif
30 
31 /* This board provides an HSE */
32 #ifndef CONFIG_BOARD_HAS_HSE
33 #define CONFIG_BOARD_HAS_HSE 1
34 #endif
35 
36 #include "periph_cpu.h"
37 #include "clk_conf.h"
38 #include "cfg_timer_tim2.h"
39 
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43 
54 static const adc_conf_t adc_config[] = {
55  { .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 1 }, /* ADC_IN1, fast */
56  { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 2 }, /* ADC_IN2, fast */
57  { .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 5 }, /* ADC_IN5, fast */
58  { .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 11 }, /* ADC_IN11, slow */
59  { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 7 }, /* ADC_IN7, slow */
60  { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 6 }, /* ADC_IN6, slow */
61  { .pin = GPIO_UNDEF, .dev = 0, .chan = 17 }, /* VBAT */
62 };
63 
64 #define VBAT_ADC ADC_LINE(6)
65 #define ADC_NUMOF ARRAY_SIZE(adc_config)
72 static const uart_conf_t uart_config[] = {
73  {
74  .dev = USART2,
75  .rcc_mask = RCC_APB1ENR_USART2EN,
76  .rx_pin = GPIO_PIN(PORT_A, 3),
77  .tx_pin = GPIO_PIN(PORT_A, 2),
78  .rx_af = GPIO_AF7,
79  .tx_af = GPIO_AF7,
80  .bus = APB1,
81  .irqn = USART2_IRQn
82  },
83  {
84  .dev = USART1,
85  .rcc_mask = RCC_APB2ENR_USART1EN,
86  .rx_pin = GPIO_PIN(PORT_A, 10),
87  .tx_pin = GPIO_PIN(PORT_A, 9),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB2,
91  .irqn = USART1_IRQn
92  },
93  {
94  .dev = USART3,
95  .rcc_mask = RCC_APB1ENR_USART3EN,
96  .rx_pin = GPIO_PIN(PORT_C, 11),
97  .tx_pin = GPIO_PIN(PORT_C, 10),
98  .rx_af = GPIO_AF7,
99  .tx_af = GPIO_AF7,
100  .bus = APB1,
101  .irqn = USART3_IRQn
102  }
103 };
104 
105 #define UART_0_ISR (isr_usart2)
106 #define UART_1_ISR (isr_usart1)
107 #define UART_2_ISR (isr_usart3)
108 
109 #define UART_NUMOF ARRAY_SIZE(uart_config)
116 static const pwm_conf_t pwm_config[] = {
117  {
118  .dev = TIM16,
119  .rcc_mask = RCC_APB2ENR_TIM16EN,
120  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
121  { .pin = GPIO_UNDEF, .cc_chan = 0 },
122  { .pin = GPIO_UNDEF, .cc_chan = 0 },
123  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
124  .af = GPIO_AF1,
125  .bus = APB2
126  }
127 };
128 
129 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
136 static const spi_conf_t spi_config[] = {
137  {
138  .dev = SPI2,
139  .mosi_pin = GPIO_PIN(PORT_B, 15),
140  .miso_pin = GPIO_PIN(PORT_B, 14),
141  .sclk_pin = GPIO_PIN(PORT_B, 13),
142  .cs_pin = GPIO_PIN(PORT_B, 12),
143  .mosi_af = GPIO_AF5,
144  .miso_af = GPIO_AF5,
145  .sclk_af = GPIO_AF5,
146  .cs_af = GPIO_AF5,
147  .rccmask = RCC_APB1ENR_SPI2EN,
148  .apbbus = APB1
149  }
150 };
151 
152 #define SPI_NUMOF ARRAY_SIZE(spi_config)
159 static const i2c_conf_t i2c_config[] = {
160  {
161  .dev = I2C1,
162  .speed = I2C_SPEED_NORMAL,
163  .scl_pin = GPIO_PIN(PORT_B, 8),
164  .sda_pin = GPIO_PIN(PORT_B, 9),
165  .scl_af = GPIO_AF4,
166  .sda_af = GPIO_AF4,
167  .bus = APB1,
168  .rcc_mask = RCC_APB1ENR_I2C1EN,
169  .rcc_sw_mask = RCC_CFGR3_I2C1SW,
170  .irqn = I2C1_ER_IRQn
171  },
172  {
173  .dev = I2C3,
174  .speed = I2C_SPEED_NORMAL,
175  .scl_pin = GPIO_PIN(PORT_A, 8),
176  .sda_pin = GPIO_PIN(PORT_A, 5),
177  .scl_af = GPIO_AF5,
178  .sda_af = GPIO_AF8,
179  .bus = APB1,
180  .rcc_mask = RCC_APB1ENR_I2C3EN,
181  .rcc_sw_mask = RCC_CFGR3_I2C3SW,
182  .irqn = I2C3_ER_IRQn
183  }
184 };
185 
186 #define I2C_0_ISR isr_i2c1_er
187 #define I2C_1_ISR isr_i2c3_er
188 
189 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
192 #ifdef __cplusplus
193 }
194 #endif
195 
196 #endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition: periph_cpu.h:48
@ PORT_C
port C
Definition: periph_cpu.h:49
@ PORT_A
port A
Definition: periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:97
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:69
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:251
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:222
Common configuration for STM32 Timer peripheral based on TIM2.
@ GPIO_AF1
use alternate function 1
Definition: cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:107
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:106
@ GPIO_AF8
use alternate function 8
Definition: cpu_gpio.h:111
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:109
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:80
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:278
ADC device configuration.
Definition: periph_cpu.h:379
gpio_t pin
pin connected to the channel
Definition: periph_cpu.h:288
I2C configuration structure.
Definition: periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:300
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219