periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 #include "clk_conf.h"
24 #include "cfg_timer_tim2.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
40 static const adc_conf_t adc_config[] = {
41  { .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 1 }, /* ADC1_IN1, fast */
42  { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 2 }, /* ADC1_IN2, fast */
43  { .pin = GPIO_PIN(PORT_A, 3), .dev = 0, .chan = 4 }, /* ADC1_IN4, fast */
44  { .pin = GPIO_PIN(PORT_A, 4), .dev = 1, .chan = 1 }, /* ADC2_IN1, fast */
45  { .pin = GPIO_PIN(PORT_A, 7), .dev = 1, .chan = 4 }, /* ADC2_IN4, fast */
46  { .pin = GPIO_UNDEF, .dev = 0, .chan = 17 }, /* VBAT */
47 };
48 
49 #define VBAT_ADC ADC_LINE(5)
50 #define ADC_NUMOF ARRAY_SIZE(adc_config)
57 static const dma_conf_t dma_config[] = {
58  { .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX */
59  { .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */
60  { .stream = 3 }, /* DMA1 Channel 4 - USART1_TX */
61  { .stream = 6 }, /* DMA1 Channel 7 - USART2_TX */
62 };
63 
64 #define DMA_0_ISR isr_dma1_channel2
65 #define DMA_1_ISR isr_dma1_channel3
66 #define DMA_2_ISR isr_dma1_channel4
67 #define DMA_3_ISR isr_dma1_channel7
68 
69 #define DMA_NUMOF ARRAY_SIZE(dma_config)
76 static const uart_conf_t uart_config[] = {
77  {
78  .dev = USART2,
79  .rcc_mask = RCC_APB1ENR_USART2EN,
80  .rx_pin = GPIO_PIN(PORT_A, 15),
81  .tx_pin = GPIO_PIN(PORT_A, 2),
82  .rx_af = GPIO_AF7,
83  .tx_af = GPIO_AF7,
84  .bus = APB1,
85  .irqn = USART2_IRQn,
86 #ifdef MODULE_PERIPH_DMA
87  .dma = 3,
88  .dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED
89 #endif
90  },
91  {
92  .dev = USART1,
93  .rcc_mask = RCC_APB2ENR_USART1EN,
94  .rx_pin = GPIO_PIN(PORT_A, 10),
95  .tx_pin = GPIO_PIN(PORT_A, 9),
96  .rx_af = GPIO_AF7,
97  .tx_af = GPIO_AF7,
98  .bus = APB2,
99  .irqn = USART1_IRQn,
100 #ifdef MODULE_PERIPH_DMA
101  .dma = 2,
102  .dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED
103 #endif
104  }
105 };
106 
107 #define UART_0_ISR (isr_usart2)
108 #define UART_1_ISR (isr_usart1)
109 
110 #define UART_NUMOF ARRAY_SIZE(uart_config)
117 static const pwm_conf_t pwm_config[] = {
118  {
119  .dev = TIM3,
120  .rcc_mask = RCC_APB1ENR_TIM3EN,
121  .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
122  { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 3 },
123  { .pin = GPIO_UNDEF, .cc_chan = 0 },
124  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
125  .af = GPIO_AF2,
126  .bus = APB1
127  },
128  {
129  .dev = TIM1,
130  .rcc_mask = RCC_APB2ENR_TIM1EN,
131  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
132  { .pin = GPIO_UNDEF, .cc_chan = 0 },
133  { .pin = GPIO_UNDEF, .cc_chan = 0 },
134  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
135  .af = GPIO_AF6,
136  .bus = APB2
137  }
138 };
139 
140 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
147 static const spi_conf_t spi_config[] = {
148  {
149  .dev = SPI1,
150  .mosi_pin = GPIO_PIN(PORT_B, 5),
151  .miso_pin = GPIO_PIN(PORT_B, 4),
152  .sclk_pin = GPIO_PIN(PORT_B, 3),
153  .cs_pin = SPI_CS_UNDEF,
154  .mosi_af = GPIO_AF5,
155  .miso_af = GPIO_AF5,
156  .sclk_af = GPIO_AF5,
157  .cs_af = GPIO_AF5,
158  .rccmask = RCC_APB2ENR_SPI1EN,
159  .apbbus = APB2,
160 #ifdef MODULE_PERIPH_DMA
161  .tx_dma = 1,
162  .tx_dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED,
163  .rx_dma = 0,
164  .rx_dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED
165 #endif
166  }
167 };
168 
169 #define SPI_NUMOF ARRAY_SIZE(spi_config)
172 #ifdef __cplusplus
173 }
174 #endif
175 
176 #endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:97
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:251
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:222
Common configuration for STM32 Timer peripheral based on TIM2.
#define DMA_CHAN_CONFIG_UNSUPPORTED
DMA channel/trigger configuration for DMA peripherals without channel/trigger filtering such as the s...
Definition: cpu_dma.h:96
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:107
@ GPIO_AF6
use alternate function 6
Definition: cpu_gpio.h:108
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:109
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:80
ADC device configuration.
Definition: periph_cpu.h:379
gpio_t pin
pin connected to the channel
Definition: periph_cpu.h:288
DMA configuration.
Definition: cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:55
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219