periph_conf.h
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1 /*
2  * Copyright (C) 2016 Fundacion Inria Chile
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 #include "clk_conf.h"
24 #include "cfg_timer_tim5.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 static const uart_conf_t uart_config[] = {
35  {
36  .dev = USART3,
37  .rcc_mask = RCC_APB1ENR_USART3EN,
38  .rx_pin = GPIO_PIN(PORT_B, 11),
39  .tx_pin = GPIO_PIN(PORT_B, 10),
40  .rx_af = GPIO_AF7,
41  .tx_af = GPIO_AF7,
42  .bus = APB1,
43  .irqn = USART3_IRQn
44  },
45  {
46  .dev = USART2,
47  .rcc_mask = RCC_APB1ENR_USART2EN,
48  .rx_pin = GPIO_PIN(PORT_A, 3),
49  .tx_pin = GPIO_PIN(PORT_A, 2),
50  .rx_af = GPIO_AF7,
51  .tx_af = GPIO_AF7,
52  .bus = APB1,
53  .irqn = USART2_IRQn
54  },
55  {
56  .dev = USART1,
57  .rcc_mask = RCC_APB2ENR_USART1EN,
58  .rx_pin = GPIO_PIN(PORT_A, 10),
59  .tx_pin = GPIO_PIN(PORT_A, 9),
60  .rx_af = GPIO_AF7,
61  .tx_af = GPIO_AF7,
62  .bus = APB2,
63  .irqn = USART1_IRQn
64  }
65 };
66 
67 #define UART_0_ISR (isr_usart3)
68 #define UART_1_ISR (isr_usart2)
69 #define UART_2_ISR (isr_usart1)
70 
71 #define UART_NUMOF ARRAY_SIZE(uart_config)
78 static const pwm_conf_t pwm_config[] = {
79  {
80  .dev = TIM3,
81  .rcc_mask = RCC_APB1ENR_TIM3EN,
82  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
83  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
84  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
85  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
86  .af = GPIO_AF2,
87  .bus = APB1
88  }
89 };
90 
91 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
98 static const spi_conf_t spi_config[] = {
99  {
100  .dev = SPI1,
101  .mosi_pin = GPIO_PIN(PORT_B, 5),
102  .miso_pin = GPIO_PIN(PORT_B, 4),
103  .sclk_pin = GPIO_PIN(PORT_B, 3),
104  .cs_pin = SPI_CS_UNDEF,
105  .mosi_af = GPIO_AF5,
106  .miso_af = GPIO_AF5,
107  .sclk_af = GPIO_AF5,
108  .cs_af = GPIO_AF5,
109  .rccmask = RCC_APB2ENR_SPI1EN,
110  .apbbus = APB2
111  },
112  {
113  .dev = SPI2,
114  .mosi_pin = GPIO_PIN(PORT_B, 15),
115  .miso_pin = GPIO_PIN(PORT_B, 14),
116  .sclk_pin = GPIO_PIN(PORT_B, 13),
117  .cs_pin = SPI_CS_UNDEF,
118  .mosi_af = GPIO_AF5,
119  .miso_af = GPIO_AF5,
120  .sclk_af = GPIO_AF5,
121  .cs_af = GPIO_AF5,
122  .rccmask = RCC_APB1ENR_SPI2EN,
123  .apbbus = APB1
124  },
125  {
126  .dev = SPI3,
127  .mosi_pin = GPIO_PIN(PORT_C, 12),
128  .miso_pin = GPIO_PIN(PORT_C, 11),
129  .sclk_pin = GPIO_PIN(PORT_C, 10),
130  .cs_pin = SPI_CS_UNDEF,
131  .mosi_af = GPIO_AF6,
132  .miso_af = GPIO_AF6,
133  .sclk_af = GPIO_AF6,
134  .cs_af = GPIO_AF6,
135  .rccmask = RCC_APB1ENR_SPI3EN,
136  .apbbus = APB1
137  }
138 };
139 
140 #define SPI_NUMOF ARRAY_SIZE(spi_config)
147 static const i2c_conf_t i2c_config[] = {
148  {
149  .dev = I2C1,
150  .speed = I2C_SPEED_NORMAL,
151  .scl_pin = GPIO_PIN(PORT_B, 8),
152  .sda_pin = GPIO_PIN(PORT_B, 9),
153  .scl_af = GPIO_AF4,
154  .sda_af = GPIO_AF4,
155  .bus = APB1,
156  .rcc_mask = RCC_APB1ENR_I2C1EN,
157  .clk = CLOCK_APB1,
158  .irqn = I2C1_EV_IRQn
159  }
160 };
161 
162 #define I2C_0_ISR isr_i2c1_ev
163 
164 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
171 static const adc_conf_t adc_config[] = {
172  { GPIO_PIN(PORT_C, 0), 10 },
173  { GPIO_PIN(PORT_C, 1), 11 },
174  { GPIO_PIN(PORT_C, 2), 12 },
175  /* ADC Temperature channel */
176  { GPIO_UNDEF, 16 },
177  /* ADC VREF channel */
178  { GPIO_UNDEF, 17 },
179 };
180 
181 #define ADC_NUMOF ARRAY_SIZE(adc_config)
188 static const dac_conf_t dac_config[] = {
189  { .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
190  { .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
191 };
192 
193 #define DAC_NUMOF ARRAY_SIZE(dac_config)
196 #ifdef __cplusplus
197 }
198 #endif
199 
200 #endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition: periph_cpu.h:48
@ PORT_C
port C
Definition: periph_cpu.h:49
@ PORT_A
port A
Definition: periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:97
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:69
static const adc_conf_t adc_config[]
ADC configuration.
Definition: periph_conf.h:251
static const pwm_conf_t pwm_config[]
Actual PWM configuration.
Definition: periph_conf.h:222
static const dac_conf_t dac_config[]
DAC configuration.
Definition: periph_conf.h:253
Common configuration for STM32 Timer peripheral based on TIM5.
@ GPIO_AF2
use alternate function 2
Definition: cpu_gpio.h:104
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:107
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:106
@ GPIO_AF6
use alternate function 6
Definition: cpu_gpio.h:108
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:109
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition: periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:80
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:278
#define CLOCK_APB1
Half AHB clock.
ADC device configuration.
Definition: periph_cpu.h:379
DAC line configuration data.
Definition: periph_cpu.h:301
gpio_t pin
pin connected to the line
Definition: periph_cpu.h:302
I2C configuration structure.
Definition: periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:300
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219