periph_conf.h
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1 /*
2  * Copyright (C) 2019 Inria
3  * 2019 Freie Universität Berln
4  * 2019 Kaspar Schleiser <kaspar@schleiser.de>
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 /* This board provides an LSE */
25 #ifndef CONFIG_BOARD_HAS_LSE
26 #define CONFIG_BOARD_HAS_LSE 1
27 #endif
28 
29 /* This board provides an HSE */
30 #ifndef CONFIG_BOARD_HAS_HSE
31 #define CONFIG_BOARD_HAS_HSE 1
32 #endif
33 
34 /* The HSE provides a 12MHz clock */
35 #ifndef CONFIG_CLOCK_HSE
36 #define CONFIG_CLOCK_HSE MHZ(12)
37 #endif
38 
39 #include "periph_cpu.h"
40 #include "clk_conf.h"
41 #include "cfg_usb_otg_fs.h"
42 
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46 
51 static const dma_conf_t dma_config[] = {
52  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
53  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
54 };
55 
56 #define DMA_0_ISR isr_dma2_stream3
57 #define DMA_1_ISR isr_dma2_stream2
58 
59 #define DMA_NUMOF ARRAY_SIZE(dma_config)
66 static const timer_conf_t timer_config[] = {
67  {
68  .dev = TIM5,
69  .max = 0xffffffff,
70  .rcc_mask = RCC_APB1ENR_TIM5EN,
71  .bus = APB1,
72  .irqn = TIM5_IRQn
73  }
74 };
75 
76 #define TIMER_0_ISR isr_tim5
77 
78 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
85 static const uart_conf_t uart_config[] = {
86  {
87  .dev = USART1,
88  .rcc_mask = RCC_APB2ENR_USART1EN,
89  .rx_pin = GPIO_PIN(PORT_B, 7),
90  .tx_pin = GPIO_PIN(PORT_B, 6),
91  .rx_af = GPIO_AF7,
92  .tx_af = GPIO_AF7,
93  .bus = APB2,
94  .irqn = USART1_IRQn,
95 #ifdef MODULE_PERIPH_DMA
96  .dma = DMA_STREAM_UNDEF,
97  .dma_chan = UINT8_MAX,
98 #endif
99  },
100 };
101 
102 #define UART_0_ISR (isr_usart1)
103 
104 #define UART_NUMOF ARRAY_SIZE(uart_config)
111 static const spi_conf_t spi_config[] = {
112  {
113  .dev = SPI1,
114  .mosi_pin = GPIO_PIN(PORT_A, 7),
115  .miso_pin = GPIO_PIN(PORT_A, 6),
116  .sclk_pin = GPIO_PIN(PORT_A, 5),
117  .cs_pin = GPIO_UNDEF,
118  .mosi_af = GPIO_AF5,
119  .miso_af = GPIO_AF5,
120  .sclk_af = GPIO_AF5,
121  .cs_af = GPIO_AF5,
122  .rccmask = RCC_APB2ENR_SPI1EN,
123  .apbbus = APB2,
124 #ifdef MODULE_PERIPH_DMA
125  .tx_dma = 0,
126  .tx_dma_chan = 3,
127  .rx_dma = 1,
128  .rx_dma_chan = 3,
129 #endif
130  }
131 };
132 
133 #define SPI_NUMOF ARRAY_SIZE(spi_config)
140 static const i2c_conf_t i2c_config[] = {
141  {
142  .dev = I2C2,
143  .speed = I2C_SPEED_NORMAL,
144  .scl_pin = GPIO_PIN(PORT_B, 10),
145  .sda_pin = GPIO_PIN(PORT_B, 11),
146  .scl_af = GPIO_AF4,
147  .sda_af = GPIO_AF4,
148  .bus = APB1,
149  .rcc_mask = RCC_APB1ENR_I2C2EN,
150  .clk = CLOCK_APB1,
151  .irqn = I2C2_ER_IRQn,
152  },
153 };
154 
155 #define I2C_0_ISR isr_i2c2_er
156 
157 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
160 #ifdef __cplusplus
161 }
162 #endif
163 
164 #endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition: periph_cpu.h:48
@ PORT_A
port A
Definition: periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
static const uart_conf_t uart_config[]
UART configuration.
Definition: periph_conf.h:39
static const spi_conf_t spi_config[]
SPI configuration.
Definition: periph_conf.h:97
static const i2c_conf_t i2c_config[]
I2C configuration.
Definition: periph_conf.h:69
static const timer_conf_t timer_config[]
All timers on board.
Definition: periph_conf.h:40
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF5
use alternate function 5
Definition: cpu_gpio.h:107
@ GPIO_AF4
use alternate function 4
Definition: cpu_gpio.h:106
@ GPIO_AF7
use alternate function 7
Definition: cpu_gpio.h:109
@ APB1
Advanced Peripheral Bus 1
Definition: periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition: periph_cpu.h:80
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: periph_cpu.h:278
#define CLOCK_APB1
Half AHB clock.
DMA configuration.
Definition: cpu_dma.h:32
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: cpu_dma.h:55
I2C configuration structure.
Definition: periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition: periph_cpu.h:300
SPI device configuration.
Definition: periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition: periph_cpu.h:338
Timer device configuration.
Definition: periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition: periph_cpu.h:265
UART device configuration.
Definition: periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition: periph_cpu.h:219